Chip error detector

Excavating

Patent

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Details

25037007, 25037014, 365154, G11C 1134, G06F 1100

Patent

active

050848739

ABSTRACT:
A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

REFERENCES:
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patent: 4130892 (1978-12-01), Gunkel, II et al.
patent: 4413327 (1983-11-01), Sabo et al.
patent: 4658352 (1987-04-01), Nagasawa
patent: 4757505 (1988-07-01), Marrington et al.
patent: 4805148 (1989-02-01), Diehl-Nagle et al.

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