Chip enable input circuit in semiconductor memory device

Details Chip enable input circuit in semiconductor memory device Chip enable input circuit in semiconductor memory device

1989-05-12

1990-11-13

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

36523006, 36523008, G11C 1134

Patent

active

049706942

ABSTRACT:
A first chip enable signal for determining the operation timing of a memory chip is supplied to a first chip enable input circuit. A second chip enable signal for selectively specifying the stand-by mode/operative mode of the memory chip and an output signal of the first chip enable input circuit are supplied to a second chip enable input circuit. The second chip enable signal is received and latched by means of the second chip enable input circuit when the first chip enable signal is set active. An internal chip enable signal is output from the second chip enable input circuit based on the latched output to set the internal circuit of the memory chip into the stand-by mode.

REFERENCES:
patent: 4679173 (1987-07-01), Sato
IC Technical Data, Toshiba MOS Memory 8th Edition, 1986, Kabushiki Kaisha Toshiba, P361-368.

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