Chip embedded package structure and fabrication method thereof

Details Chip embedded package structure and fabrication method thereof Chip embedded package structure and fabrication method thereof

2006-03-28

2009-06-30

Thai, Luan C (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Bidirectional rectifier with control electrode

C257S126000, C257S106000, C257S127000

Reexamination Certificate

active

07554131

ABSTRACT:
A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the cavity. At least one semiconductor chip is mounted via its non-active surface on the adhesive layer and received in the cavity. A protection layer is formed on an active surface of the semiconductor chip. A conductive layer is formed on a top surface of the carrier board, the protection layer and the cavity. A patterned resist layer is applied on the conductive layer and is formed with an electroplating opening at a position corresponding to a gap between the cavity and the semiconductor chip. An electroplating process is performed to form a metal layer in the electroplating opening, such that the semiconductor chip can be effectively fixed in the cavity by the metal layer.

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patent: 5583377 (1996-12-01), Higgins, III
patent: 6518885 (2003-02-01), Brady et al.
patent: 6664617 (2003-12-01), Siu
patent: 6900535 (2005-05-01), Zhou

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