Chip embedded package structure

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S797000, C257SE23179, C257SE23176, C257SE23064

Reexamination Certificate

active

10994043

ABSTRACT:
A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.

REFERENCES:
patent: 3868724 (1975-02-01), Perrino
patent: 6154366 (2000-11-01), Ma et al.
patent: 6166433 (2000-12-01), Takashima et al.
patent: 6475877 (2002-11-01), Saia et al.
patent: 6864165 (2005-03-01), Pogge et al.
patent: 7026079 (2006-04-01), Louwet et al.
patent: 2002/0011650 (2002-01-01), Nishizawa et al.
patent: 2003/0043565 (2003-03-01), Juang
patent: 2003/0155908 (2003-08-01), Ohazama

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