Chip edge interconnect overlay element

Details Chip edge interconnect overlay element Chip edge interconnect overlay element

1992-03-04

1993-07-20

Thompson, Gregory D.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

174254, 174268, 257668, 257712, 257777, 361398, 361417, 361419, H05K 720

Patent

active

052299163

ABSTRACT:
A chip overlay element is formed of a flexible substrate of polymer having electrically conductive material applied to one side thereof and circuitized to form signal lines. A metal stiffener/heat spreader is laminated to the polymer on the opposite side of the conductor. I/Os are formed on one end of the signal lines of the circuitized layer (near the end of the overlay element) and interconnection pads, bumps, or the like are formed on the opposite end (near the center of the element). The metal stiffener is then etched to form three distinct areas. The chip edge is then placed on the center metal stiffener area and bonded, with the other two stiffener areas being bent around the chip and bonded to the corresponding chip sides. The original I/Os are then electrically connected to the I/Os formed on the signal lines of the overlay element.

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IBM TDB "High Density Flexible Connector", vol. 32, No. 7, Dec. 1989, pp. 344-345.

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