Chip carrier with reduced interference signal sensitivity

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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Details

C257S211000, C257S266000, C257S635000, C257S637000, C361S760000, C361S761000, C361S763000, C361S777000

Reexamination Certificate

active

07911026

ABSTRACT:
Carrier including:a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

REFERENCES:
patent: 6518670 (2003-02-01), Mandelman et al.
patent: 6970362 (2005-11-01), Chakravorty
patent: 7557014 (2009-07-01), Okamoto et al.
patent: 2005/0023664 (2005-02-01), Chudzik et al.
patent: 2005/0263874 (2005-12-01), Shimizu et al.
patent: WO 2005/104149 (2005-11-01), None

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