Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1996-03-22
1998-11-17
Karlsen, Ernest F.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324750, 324754, G01R 31308
Patent
active
058381597
ABSTRACT:
Disclosed are a die carrier and associated method for conducting probe beam tests on chips designed to be packaged in flip-chip packages. The die carrier is a specially modified membrane type carrier that includes a probe access region, such as an opening, in the membrane. A die to be tested is mounted in the die carrier such that its I/O pads make electrical contact with corresponding bump contacts on the membrane. The die/carrier assembly is then mounted in a test socket provided on a chip testing apparatus such that electrical I/O signals can be provided to and from an external test circuit. While the die is being electrical tested, a probe beam is directed through the probe access region and onto the chip active surface. In this manner, the chip active surface is probed while exposed to electrical stimulus.
REFERENCES:
patent: 5519658 (1996-05-01), Uda et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5583445 (1996-12-01), Mullen
Estes, Richard and Kulesza, Frank, "Environmental and Reliability Testing of Conductive Polymer Flip Chip," American Superconductor Corporation, (month unavailable) 1993.
Prokopchak, Lina, AEHR Test Systems KGD Product Manager and Wrenn, James, AEHR Test Systems Chief KGK Scientist, "Development of a Burn-in and Test Process for Producing Known-Good-Die," KGD--P/N 405-56001-00, (Prior to Aug. 1995).
Prokopchak, Lina, AEHR Test Systems, Presented at ITC, Washington D.C., "Development of a Solution for Achieving Known-Good-Die," Sep. 1994.
Product Brochure, DiePak .TM. Known Good Die Solutions, (Prior to Aug. 1995).
Kulesza, Frank W. and Estes, Richard H., Solderless Flip Chip Technology, Hybrid Circuit Technology, Feb. 1992.
Kulesza, Frank W., Estes, Richard H., and Spanjer, Keith, "A Screen-Printable Polyimide Coating for Silicon Wafers", Jan. 1988 edition of Solid State Technology.
Product Brochure, PFC .TM., Epoxy Technology, Inc., Chip Interconnect Comparison (Prior to Aug. 1995).
Estes, Richard H., "Fabrication and Assembly Processes for Solderless Flip Chip Assemblies", ETI, Jun. 1993.
Karlsen Ernest F.
Sun Microsystems Inc.
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