Chip carrier substrate with a land grid array and external...

Details Chip carrier substrate with a land grid array and external... Chip carrier substrate with a land grid array and external...

2007-07-17

2007-07-17

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257SE23067

Reexamination Certificate

active

11128682

ABSTRACT:
A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

REFERENCES:
patent: 6461895 (2002-10-01), Liang et al.
patent: 6747352 (2004-06-01), Huemoeller et al.
patent: 7045897 (2006-05-01), Egitto et al.
patent: 2002/0145203 (2002-10-01), Adae-Amoakoh et al.
patent: 2002/0173070 (2002-11-01), Bolken et al.
patent: 2003/0164543 (2003-09-01), Kheng Lee
patent: 2006/0022303 (2006-02-01), Desai et al.

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