Chip carrier having copper pattern plated with gold on one surfa

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

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361768, 361777, 361760, 174 522, 174260, 174263, 257779, 257786, 257787, H05K 702, H05K 118, H01L 2328

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active

054466253

ABSTRACT:
A chip carrier (20) includes a substrate (11) having a first copper pattern (12) deposited on a first surface (13), and a second copper pattern (14) deposited on a second surface (16). The second copper pattern (14) is plated with a metallic material to form wire bondable areas (18) on the second copper pattern (14), however, the first copper pattern (12) is substantially devoid of the metallic material. A device (21) is wire bonded to the wire bondable areas (18) of the second copper pattern (14), and a protective covering (23) covers the wire bondable areas (18).

REFERENCES:
patent: 5075965 (1991-12-01), Carey et al.
patent: 5153051 (1992-10-01), Dorinski
patent: 5162144 (1992-11-01), Brown et al.
patent: 5241133 (1993-08-01), Mullen, III et al.
Electronic Packaging and Production, A Cahners Publication, May 1992.
Microstructures and Mechanical Properties of Aging Materials, A Publication of TMS, Minerals, Metals & Materials, Proceedings of a Symposium sponsored by the Minerals, Metals and Materials Socciety held in conjunction with ASM International, pp. 431-442. Nov. 2-5, 1992.

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