Chip carrier

Details Chip carrier Chip carrier

1991-04-25

1992-02-04

LaRoche, Eugene R.

357 55, 357 72, 357 66, 357 73, H01L 2348

Patent

active

050863347

ABSTRACT:
An integrated circuit chip carrier having reduced and predicable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.

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"EP & P News in Electronics Manufacturing", by Robert Keeler, Senior Editor.
File History of U.S. Pat. No. 4,931,854 to Yonemasu et al.
Robert Keeler, "Multichip Module Shaves Lines to 10 Microns," EP & P News in Electronics Manufacturing, (undated).

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