Chip arrangement and method of manufacturing a chip arrangement

Details Chip arrangement and method of manufacturing a chip arrangement Chip arrangement and method of manufacturing a chip arrangement

2011-06-14

2011-06-14

Thai, Luan C (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S774000, C257SE27137, C257SE27144, C257SE27161

Reexamination Certificate

active

07960843

ABSTRACT:
A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side.

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patent: 2008/0128882 (2008-06-01), Baek et al.

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