Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Patent
1996-08-27
1997-09-16
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
257623, 257629, 257624, H01L 2360, H01L 2348
Patent
active
056684010
ABSTRACT:
A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.
REFERENCES:
patent: 4618262 (1986-10-01), Maydan et al.
patent: 4967259 (1990-10-01), Takagi
patent: 5151584 (1992-09-01), Ebbing et al.
patent: 5151766 (1992-09-01), Huppi
patent: 5290711 (1994-03-01), Yanagisawa
patent: 5453637 (1995-09-01), Fong-Chun et al.
patent: 5462636 (1995-10-01), Chen et al.
Chao Ying Chen
Shen Chih-Heng
Saile George O.
Taiwan Semiconductor Manufacturing Company Ltd
Thomas Tom
Williams Alexander Oscar
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