Chemically removable Cu CMP slurry abrasive

Details Chemically removable Cu CMP slurry abrasive Chemically removable Cu CMP slurry abrasive

1998-11-25

2001-01-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S687000, C134S001300

Utility Patent

active

06169034

ABSTRACT:

TECHNICAL FIELD
The present invention relates semiconductor devices comprising copper (Cu) and/or Cu alloy interconnection patterns. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed interdielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trenches typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an interdielectric layer on a conductive layer comprising at least one conductive pattern, forming an opening in the interdielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interdielectric layer can be removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As the length of metal interconnects increases, and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect increases. As design rules are reduced to about 0.18 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for Al in VLSI interconnection metallizations. Cu is relatively inexpensive, easy to process, has a lower resistivity than Al, and has improved electrical properties vis-{grave over (a)}-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the dielectric interlayer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium tungsten (TiW), tungsten nitride (WN), and silicon nitride (Si
3
N
4
) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology. For example, conventional practices comprise forming a damascene opening in an interdielectric layer and depositing a barrier layer, such as Ta or TaN, lining the opening and on the interdielectric layer. Cu or a Cu alloy is then deposited on the barrier layer filling the opening. CMP is then conducted employing an abrasive slurry. Conventional CMP slurries are typically aqueous suspensions comprising a particulate abrasive, such as alumina, an organic dispersant, and a suitable oxidizing agent. Other adjuvants can be employed to improve dispersibility or enhance performance. In CMP Cu and Cu alloy metallization, the CMP slurry typically contains a relatively large amount of a relatively hard particulate material, such as alumina, e.g. about 2 to about 3 wt. % of alumina. However, during conventional CMP, it was found that the planarized Cu or Cu alloy surface undergoes abrasion, i.e., scratching. In addition, conventional practices typically comprises mechanically removing remaining or residual slurry particles after CMP, as by buffing with water on a secondary platen buff pad, or by scrubbing with a polyvinyl acetate (PVA) foam brush material on a wafer scrubbing tool. Such mechanical removal of slurry particles is not particularly effective and may cause further scratching of the Cu surface.
Accordingly, there exists a need for CMP Cu methodology which enables a high degree of planarization without surface abrasion and which facilitates removal of residual abrasive slurry particles subsequent to CMP with a high degree of efficiency.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device comprising CMP Cu metallization to achieve a smooth surface and facilitate efficient removal of residual slurry particles subsequent to CMP.
Additional advantages and other features of the present invention are set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: depositing a layer of copper (Cu) or a Cu alloy; chemical mechanical polishing (CMP) the deposited Cu or Cu alloy with a slurry containing a particulate abrasive material; and removing remaining particulate material after CMP with a dilute acidic solution.
Embodiments include forming damascene openings in an interdielectric layer, depositing a barrier layer, such as Ta or TaN, lining the openings and on the interdielectric layer, depositing Cu or a Cu alloy on the barrier layer filling the opening, planarizing by CMP employing a slurry containing particulate magnesium o

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