Coating apparatus – Gas or vapor deposition
Reexamination Certificate
1999-05-14
2001-12-11
Everhart, Caridad (Department: 2825)
Coating apparatus
Gas or vapor deposition
C118S7230AN, C118S716000, C438S687000, C438S681000, C438S677000
Reexamination Certificate
active
06328804
ABSTRACT:
BACKGROUND OF THE INVENTION
Conventional integrated circuits, or “chips,” are formed from a flat surface semiconductor wafer. The semiconductor wafer is typically manufactured in a semiconductor material manufacturing facility and then provided to an integrated circuit fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
With respect to a conventional semiconductor manufacturing and fabrication facility, the facility is relatively expensive to operate due to the enormous effort and expense required for creating flat silicon wafers and chips. For example, manufacturing of wafers requires several high-precision steps including creating rod-form single crystal semiconductor material; precisely cutting ingots from the semiconductor rods; cleaning and drying the cut ingot sections; manufacturing a large single crystal from the ingots by melting them in a quartz crucible; grinding, etching, and cleaning the surface of the crystal; cutting, lapping and polishing wafers from the crystal; and heat processing the wafers. Moreover, the wafers produced by the above processes typically have many defects which are largely attributable to the difficulty in making a single, highly pure crystal due to the above cutting, grinding and cleaning processes as well as due to various impurities, including oxygen, associated with containers used during the forming of the crystals. These defects become more and more prevalent as feature sizes of integrated circuits formed on these wafers become smaller.
Another major problem associated with modern fabrication facilities for flat chips is that they require extensive and expensive equipment. For example, dust-free clean rooms and precisely-controlled manufacturing and storage areas are necessary to prevent the wafers and chips from defecting and warping. Also, these types of fabrication facilities suffer from a relatively inefficient throughput as well as an inefficient use of the silicon. For example, facilities using in-batch manufacturing, where the wafers are processed by lots, must maintain huge inventories to efficiently utilize all the equipment of the facility. Also, because the wafers are round, and the completed chips are rectangular, the peripheral portion of each wafer cannot be used.
Still another problem associated with modern fabrication facilities is that they do not produce chips that are ready to use. Instead, there are many additional steps that must be completed, including cutting and separating chips from the wafer; assembling each chip to a lead frame which includes wire bonding, plastic or ceramic molding and cutting and forming the leads, positioning assembled chip onto a printed circuit board; and mounting the assembled chips to the printed circuit board. The cutting and assembly steps introduce many errors and defects due to the precise requirements of such operations. In addition, the positioning and mounting steps are naturally two-dimensional in character, and therefore do not support curved or three dimensional areas.
Therefore, due to these and various other problems, only a few companies in the world today can successfully manufacture conventional flat chips. Furthermore, the chips must bear a high price to cover the costs of manufacturing, as well as the return on initial capital and investment.
In addition to the above, one technology which may be used during semiconductor chip manufacturing includes chemical vapor deposition (CVD) technology. Existing chemical vapor deposition (CVD) technology uses low pressure in a vacuum processing chamber to form a metal layer, e.g., copper or aluminum, on large diameter silicon wafers. A low pressure is required for obtaining a uniform layer over the wafer surface, since the wafer surface resides in the same position during deposition of the metal layer. In addition, vacuum sputtering processes are traditionally used in the semiconductor industry for making metal interconnects.
In co-pending U.S. patent application Ser. No. 08/858,004 filed on May 16, 1997, entitled “Spherical Shaped Semiconductor Integrated Circuit” and assigned to the same assignee as the present application, incorporated herein by reference, a method and system for manufacturing spherical-shaped semiconductor integrated circuit devices is disclosed. The manufacturing of spherical shaped semiconductor integrated circuit devices as disclosed in U.S. patent Ser. No. 08/858,004 involves a continuous atmospheric semiconductor IC manufacturing process. As a result, deposition of metals using low pressure CVD techniques, as disclosed in the art with respect to flat semiconductor substrates, is incompatible for use in the manufacture of spherical shaped semiconductor substrate. An atmospheric CVD process for coating spherical shaped semiconductor substrates and integrated circuits would thus be desirable.
U.S. patent Ser. No. 09/113,671 filed Jul. 10, 1998, assigned to the same assignee as the present application and incorporated herein by reference, provides a method for metal-organic chemical vapor deposition (MO CVD) of a metal layer upon a spherical substrate at atmospheric pressure. A spherical substrate is pretreated with a vapor of a first precursor in preparation for a deposition of a metal layer. The step of pretreating the spherical substrate includes exposing the surface of spherical substrate to the first precursor vapor to form nucleation sites for a subsequent metal deposition, the first precursor including a liquid tetrakisdimethylamino-titanium (TDMAT) precursor. This step may also be described as a chemical vapor deposition of titanium nitride (TiN CVD). The pretreated spherical substrate is then exposed to a thermally dissociated precursor of metal for depositing the metal layer onto the spherical substrate. The exposure to the thermally dissociated precursor of metal provides a uniformly deposited metal layer coverage over the pretreated spherical substrate, wherein the step of exposing the pretreated spherical substrate further includes using a thermally dissociated liquid dimethyl-aluminum hydride (DMAH) precursor. This step may also be described as a chemical vapor deposition of aluminum (Al CVD). Next, the deposited metal layer is then annealed and cooled.
Although the above described method for MO CVD works well for its intended purpose, it has drawbacks associated with a continuous, pipelined fabrication operation. Specifically, the thermally dissociated precursor of metal for depositing the metal layer onto the spherical substrate also deposits a metal layer on the chamber used to perform this operation. As a result, the chamber must be cleaned on a periodic basis.
What is desired is a method for MO CVD that reduces the deposits of metal on the chamber, thereby requiring less frequent cleaning.
Further, what is desired is a method for MO CVD that readily accommodates copper (Cu) deposition (Cu CVD).
SUMMARY OF THE INVENTION
The present embodiments include a method and system for depositing thin films on the surface of spherical shaped semiconductor substrates. In one embodiment, the method performs chemical vapor deposition of a metal layer upon the semiconductor spherical substrate by using a reactor made of a material such as quartz (SiO
2
). The semiconductor spherical substrate moves through the reactor where it is heated by a heater such as an infrared heater. The heater utilizes an infrared power source operating at a wavelength where the power is substantially absorbed by the semiconductor spherical substrate and is substantially transmitted by the quartz. For example, the wavelength may be between 1 and 3 microns.
In another embodiment, the metal layer includes one of either aluminum or copper. Also, the semiconductor spherical substrate may spin inside the reactor to facilitate the metal deposition.
REFERENCES:
patent: Re. 314
Miller Jeffrey Ned
Murzin Ivan Herman
Tapiawala Ajay
Ball Semiconductor Inc.
Everhart Caridad
Haynes and Boone LLP
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