Chemical vapor deposition methods

Details Chemical vapor deposition methods Chemical vapor deposition methods

2001-03-01

2003-07-22

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S935000, C438S758000

Reexamination Certificate

active

06596641

ABSTRACT:

TECHNICAL FIELD
This invention relates to chemical vapor deposition methods and to methods of etching a contact opening over a node location on a semiconductor substrate.
BACKGROUND OF THE INVENTION
The invention primarily grew out needs for making highly reliable, high density dynamic random access memory (DRAM) contacts, although the invention is in no way so limited. Advanced semiconductor fabrication is employing increasing vertical circuit integration as designers continue to strive for circuit density maximization. Such typically includes multi-level metalization and interconnect schemes.
Electrical interconnect techniques typically require electrical connection between metals or other conductive layers, or regions, which are present at different elevations within the substrate. Such interconnecting is typically conducted, in part, by etching a contact opening through insulating material to the lower elevation of a desired node contact, for example of a conductive layer or conductive region. The significant increase in density of memory cells and vertical integration places very stringent requirements for contact fabrication technology. The increase in circuit density has resulted in narrower and deeper electrical contact openings between layers within the substrate, something commonly referred to as increasing aspect ratio, which is the ratio of maximum opening height to minimum opening width. Increasing aspect ratios make it difficult to complete etches to desired node locations.
For example, one typical contact etch includes the etch to a substrate diffusion region formed within a semiconductive material which is received between a pair of field effect transistor gate lines. The gate lines are typically encapsulated in a silicon nitride and/or undoped silicon dioxide material. A planarized layer of borophosphosilicate glass (BPSG) is typically provided over the field effect transistors and through which a contact opening to the substrate will be etched. Further, a very thin undoped silicon dioxide layer is typically provided intermediate the BPSG layer and the underlying substrate material to shield from diffusion of the boron and phosphorus dopants from the BPSG layer into underlying substrate material. Additionally or alternately, a thin silicon nitride layer might also be provided. An antireflective layer might also be provided over the BPSG. The layers are typically masked, for example with photoresist, and a contact opening is formed through the mask over the underlying layers over the diffusion region to which contact is desired. The antireflective coating is then etched, followed by an etch conducted through the BPSG which is substantially selective to the silicon nitride layer, undoped oxide and underlying silicon substrate such that the etch is typically referred to as a substantially self-aligned contact etch. An example dry anisotropic etching chemistry for the etch includes a combination of CHF
3
, CF
4
, CH
2
F
2
and Ar. The typical intervening undoped silicon dioxide layer between the underlying substrate and the BPSG will typically also be etched through in spite of a poor etch rate compared to BPSG, principally due to the extreme thinness of this layer. Further, if silicon nitride is used in addition or in place of the undoped silicon dioxide layer, if would typically be separately etched. At the conclusion of the etch or etches, a native oxide might grow, which could be stripped with a dilute HF solution prior to plugging the contact opening with conductive material(s).
When the aspect ratio of the contact opening being etched through the BPSG was sufficiently below 4:1, a single etch chemistry for the BPSG was typically suitable to clear the BPSG and a thin undoped silicon oxide layer all the way to the diffusion region to outwardly expose the same, assuming silicon nitride was not present. However, as the aspect ratio of the contact opening through the BPSG approached and exceeded 4:1, it was discovered in some instances that the subject chemistry, and other attempted chemistries, were not sufficient to enable clearing the doped oxide dielectric material utilizing a single chemistry and a single etching step.
These are the circumstances which motivated the invention, although the results and objectives are in no way to be perceived as claim limitations unless such are specifically provided in the accompanying claims. The invention also has applicability outside of the problems from which it spawned, with the invention only being limited by the accompanying claims as literally worded without writing limitations or interpretations into the claims from the specification or drawings, and as appropriately interpreted in accordance with the doctrine of equivalents.
SUMMARY
The invention comprises chemical vapor deposition methods and methods of etching a contact opening over a node location on a semiconductor substrate. In but one implementation, a chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate.
In one implementation, a method of etching a contact opening over a node location on a semiconductor substrate includes forming a dielectric first layer over a node location. An oxide second layer having plural dopants therein is formed over the dielectric first layer. The oxide second layer has an innermost portion and an outer portion. The outer portion has a higher concentration of one of the dopants than any concentration of the one dopant in the innermost portion. Using a single dry etching chemistry, a contact opening is etched into the outer and innermost portions of the oxide second layer to proximate the dielectric first layer over the node location. Etching is conducted into the dielectric first layer through the contact opening to proximate the node location.
In one implementation, a method of etching a contact opening over a node location on a semiconductor substrate includes forming a dielectric first layer over a node location. An oxide second layer having plural dopants therein is formed over the dielectric first layer. The oxide second layer has an innermost portion and an outer portion. The innermost portion has a higher concentration of one of the dopants than any concentration of the one dopant in the outer portion. Using a single dry etching chemistry, a contact opening is etched into the outer and innermost portions of the oxide second layer to proximate the dielectric first layer over the node location. Etching is conducted into the dielectric first layer through the contact opening to proximate the node location.
Other implementations are contemplated.


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