Chemical planarization performance for copper/low-k...

Details Chemical planarization performance for copper/low-k... Chemical planarization performance for copper/low-k...

2006-07-04

2006-07-04

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S643000, C257S759000, C257S760000

Reexamination Certificate

active

07071539

ABSTRACT:
An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

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patent: WO 00/31183 (2000-06-01), None
patent: WO 02/083327 (2001-10-01), None

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