Chemical-mechanical polishing slurry for polishing of copper...

Details Chemical-mechanical polishing slurry for polishing of copper... Chemical-mechanical polishing slurry for polishing of copper...

2002-02-22

2004-11-23

Marcheschi, Michael (Department: 1755)

Abrasive tool making process, material, or composition

With inorganic material

C051S298000, C051S293000, C106S003000, C252S079100

Reexamination Certificate

active

06821309

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable
FIELD OF THE INVENTION
This invention relates to a slurry and method for chemical-mechanical polishing of a copper or silver containing film.
BACKGROUND
Reductions in semiconductor device dimensions provide higher densities and improved performance for integrated circuits. In many integrated electronic devices, millions of discrete elements, such as transistors, resistors and capacitors, are interconnected. Due to an increase in device density provided by scaling of semiconductor processes to improve circuit performance, it is no longer generally possible to utilize a single metal interconnect level. Single level interconnects result in significant parasitic resistance which can adversely affect device performance, particularly the dynamic performance of the integrated circuit.
Copper has become an increasingly popular choice for interconnect metal and has begun replacing aluminum in certain applications. Copper is much more conductive than aluminum, allowing finer wires having lower resistive losses. Copper is also significantly less vulnerable to electromigration than aluminum and less likely to fracture under stress. Electromigration is the drift of metal atoms when a conductor carries high current densities, and can create reliability problems through generation of voids and other defects.
Although, copper provides advantages over aluminum, it has at least one major disadvantage. Copper is poisonous to silicon since it readily diffuses into silicon and causes deep-level defects. Therefore, copper must be isolated from silicon, usually through use of a suitable barrier layer.
Multilevel metallization structures have been developed which include an interconnection structure having several levels of metallization separated by thin insulating layers. Metal plugs are used to connect the different metal levels to one another. Presently, aluminum alloys (e.g. Al/Si/Cu) are still commonly used for the metal interconnect, while tungsten is generally used for plug structures as the material of choice for interconnecting two levels of metals. Aluminum and its alloys are generally dry etched, such as reactive ion etching and plasma etching. However, dry etching of copper is not currently feasible. Accordingly, when copper and its alloys are used instead of conventional aluminum or aluminum alloys as an interconnection material, alternative techniques are employed to define the copper lines.
For example, a damascene process together with chemical-mechanical polishing (CPM) can be used to define copper lines. In a damascene process, trenches are etched in a dielectric material, such as silicon dioxide (SiO
2
). A barrier material is then deposited, generally by sputtering. Copper is then deposited typically using electrodeposition techniques (e.g. electroplating) to fill the barrier lined trenches. In the case of electrodeposition of copper onto a silicon wafer, the wafer is typically coated with a thin conductive layer of copper (seed layer) to produce electrically conductive surfaces before being immersed in a solution containing cupric ions. The copper seed layer is preferably extremely thin, but must still be continuous across all features on the wafer surface to maximize deposition of copper on via sidewalls while minimizing the layer thickness on the bottom of the features and on the field of the wafer. The copper film is then removed by CMP to define the copper lines.
CMP combines both chemical action and mechanical forces and is commonly used to remove metal deposits in damascene processes, remove excess oxide in shallow trench isolation steps, and to reduce topography across a dielectric region. Components required for CMP include a chemically reactive liquid medium and a polishing surface to provide the mechanical control required to achieve planarity. Either the liquid or the polishing surface may contain nano-size inorganic particles to enhance the reactive and mechanical activity of the process. CMP is the only technique currently known for producing die level flatness required for sub 0.5 &mgr;m devices and is considered a requirement for the production of sub 0.2 &mgr;m device structures and state-of-the-art metal interconnect schemes.
Metals can also be used to form the gate electrode of certain devices. In this case, the metal gate provides the electrical pathway for switching the device. In the case of a MOS transistor, the gate dielectric is typically silicon dioxide while the typical gate electrodes presently used are formed from heavily doped polysilicon. Alternative gate dielectrics having improved properties may soon replace SiO
2
. For example, novel high dielectric constant materials such as yttria stabilized zirconia (YSZ), hafnia, lanthanum oxide, and certain silicates are expected to find increasing use for future high performance applications. To use these gate dielectrics more efficiently, gate electrode materials such as Ta, Cu, and Pt may also become used.
Other possible metallic materials may include Os, Ru, TiN, TaSiN, IrO
2
, RuO
2
and other conducting oxides such as tin oxide (SnO
2
), indium tin oxide, and related mixtures and alloys. Copper may be deposited on top of these material systems. Besides the use of copper in interconnects for CMOS devices and gate structures in high dielectric constant materials, there may be number of emerging applications such as ferroelectric random access memory devices (FeRAM), tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) devices where copper is deposited on a metal or a dielectric structure. In a FeRAM, copper may be used as the interconnecting metal or as sandwich metal layer on a gate electrode system. In a TMR or a GMR device, copper can be used as a back terminal, front end terminal or an electrode on a multilayer magnetic
on-magnetic structure. To create these specific structures it is also essential to remove copper selectively from the surface, but not remove the underlying dielectric or metallic material. Other examples of possible uses of copper may lie in the integration of MRAM (magnetic random access memory) devices for non-volatile storage.
In the future, copper may be replaced by silver. Silver has higher electrical conductivity as compared to copper, and should provide comparable electromigration resistance which makes it ideal for interconnect and related applications. The electromigration capability of silver has been shown to improve significantly when the silver layer is encapsulated with a thin film.
FIG. 1
shows a schematic view of the steps in a copper damascene CMP process. A low dielectric constant material disposed on a silicon wafer is patterned by suitable etching to form a plurality of trenches
110
as shown in FIG.
1
(
a
). A diffusion barrier layer
120
, such as Ti, Ta or TaN, is then applied to cover the wafer surface, including the trenches
110
as shown in FIG.
1
(
b
). A copper or copper alloy layer
130
is then deposited, by a method such as electroplating. (FIG.
1
(
c
)). The copper or copper alloy layer is isolated from the remainder of the circuit by the barrier layer
120
. Copper disposed over dielectric plateaus is commonly referred to as overburden metal
131
.
A CMP process can then be used to define the copper layer through an essentially planar removal process. The CMP process proceeds to remove the copper layer sufficient to remove the overburden portion
131
to expose the barrier layer in the overburden regions
131
to produce the structure
140
which is shown in FIG.
1
(
d
). A second CMP step, generally using a different slurry solution as compared to the copper CMP process, is then used to polish the barrier layer and produce the completed structure
150
which is shown in FIG.
1
(
e
). This process can be repeated to produce multiple copper or other conductor levels to form a plurality of interconnect or other levels.
FIG. 2
shows a schematic view of a CMOS transistor
200
having a metal gate formed from a damascene/CMP process. Transistor
200
is

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