Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-03-23
2001-05-08
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C216S089000, C438S693000, C438S750000, C438S754000
Reexamination Certificate
active
06228771
ABSTRACT:
FIELD OF INVENTION
This invention relates to a chemical mechanical polishing (CMP) process for low dishing of metal lines embedded in a dielectic layer during semiconductor wafer fabrication, and more particularly, to a CMP process having two successive polishing steps for providing metal lines as individual lines in trenches on an insulation layer, substantially without pronounced attendant dishing. As used herein, “semiconductor wafer” means any microelectronic device, substrate, chip or the like, e.g., of silicon, used to provide an integrated circuit or other related circuitry structure, and in particular capable of forming an arrangement of metal lines on an insulation layer thereof.
BACKGROUND OF THE INVENTION
In fabricating microelectronic semiconductor devices and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are provided in selective sequence on the wafer. To maximize device component integration in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are used for denser packing of components per very large scale integration (VLSI) technique, e.g., at sub-micron dimensions, i.e., below 1 micron or 1,000 nanometers (nm) or 10,000 angstroms (A).
A CMP process is known for providing a damascene (inlaid) pattern, i.e., an arrangement of closely spaced apart individual metal lines, e.g., of copper (Cu), unconnected to each other and disposed in a like arrangement of closely spaced apart trenches, in an insulation layer, e.g., an oxide layer such as of silicon dioxide (SiO
2
), in the IC fabrication of a semiconductor wafer, e.g., of silicon (Si).
A liner layer forming an adhesion promoting diffusion barrier is optionally disposed between a lower insulation layer such as an oxide layer containing the trenches and an upper metal layer used to provide the individual metal lines in the trenches. When the liner layer is absent, the known CMP process is a one-phase process comprising a one-step metal layer CMP process, and when the liner layer is present, the known CMP process is a two-phase process comprising a one-step metal layer CMP process as a first phase, e.g., of about 210 seconds (3.5 minutes) polishing time, and a liner layer removing CMP process as second phase, e.g., of about 90 seconds (1.5 minutes) polishing time, for a total process (polishing) time of about 300 seconds (5 minutes).
For instance, the wafer, e.g., a circular disc of about 8 inches (200 mm) diameter, has a copper layer disposed on the oxide layer so as to provide an arrangement of wide metal lines, i.e., metal lines having a width of at least about 2 microns, such as about 2-100 microns, in the arrangement of trenches of the oxide layer. The wafer is polished in conventional manner by a rotating polishing pad, e.g., at about 20-100 rpm, such as about 55 rpm. The first phase CMP is effected under a polishing pressure downforce of about 4.5 psi for a total first phase CMP process (polishing) time of about 210 seconds (3.5 minutes), to an extent for providing the wide metal lines as individual lines unconnected to each other, i.e., by the metal (copper) of the copper metal layer.
Specifically, sufficient overpolishing is used to assure complete removal of the metal layer portion which overlies the metal lines and also the metal layer portion which is disposed over the adjacent field areas of the oxide layer outwardly of the metal lines. This overpolishing assures that the individual metal lines are no longer connected to each other through the overlying metal layer portion.
However, the so polished wafer suffers from pronounced attendant dishing in the damascene pattern area containing the metal line arrangement in the trench arrangement. Dishing is the formation of a concave depression, e.g., in the arrangement of metal lines in the arrangement of trenches, which occurs during CMP with the rotating polishing pad, and becomes increasingly pronounced as polishing pressure downforce increases, which at the same time increases the process speed (polishing rate).
On the one hand, copper CMP is one of the most costly processes in semiconductor fabrication. Any polishing rate increase (polishing time reduction) would thus be desirable to improve the competitiveness of this CMP process. On the other hand, dishing, which generally increases with increasing polishing pressure, is an important process parameter that directly controls the sheet resistance (RS) performance of each individual wide metal line. In this regard, RS is the quotient of the resistivity of the metal material divided by the metal line thickness (height) and is a measure of the amount of current the line can carry. Of course, such metal line height decreases as the dishing depth increases, and the smaller the metal line cross sectional area, the smaller the current the line can carry.
It is desirable to have a CMP process for forming an arrangement of closely spaced apart metal lines, especially wide metal lines, e.g., of copper, as individual metal lines in a like arrangement of trenches in an insulation layer of a semiconductor wafer, which provides an increase in polishing rate (shorter polishing time) without an increase in dishing or a reduction in dishing while retaining a high polishing rate.
SUMMARY OF THE INVENTION
The foregoing drawbacks are obviated in accordance with the present invention by providing a two-step chemical mechanical polishing (CMP) process for low dishing of metal lines in semiconductor wafer fabrication, to form an arrangement (damascene pattern) of closely spaced apart metal lines, especially wide metal lines, e.g., of copper, as individual metal lines in a like arrangement of trenches in an insulation layer on the wafer, substantially without pronounced attendant dishing.
According to the invention, the successive two-step CMP process for low dishing of closely spaced apart metal lines formed in closely spaced apart trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprises:
a first step of chemically mechanically polishing a metal layer disposed on the insulation layer and having a lower portion located in the trenches of the insulation layer for forming metal lines and an upper portion overlying the lower portion;
the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high (fast) rate (comparatively short polishing time) the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches; and
a second step of continuing the polishing at a selectively lower downforce sufficient to remove at a corresponding lower (slower) rate the lower portion of the metal layer with attendant minimized or reduced dishing to an extent for providing the metal lines as individual metal lines correspondingly disposed in the trenches.
Desirably, the first step is effected at a high downforce of about 3-8 psi, and the second step is effected at a lower downforce of about 1-5 psi, and the total polishing time is about 120-480 seconds (2-8 minutes).
Typically, the wafer comprises silicon, the insulation layer comprises silicon dioxide and the metal layer comprises copper. The insulation layer may have a thickness of about 100-2000 nm (0.1-2 micron), and the metal layer may have a thickness of about 200-2000 nm (0.2-2 microns).
The polishing may be effected using a chemical mechanical polish comprising an alumina abrasive and ferric nitride as oxidizer.
In particular, a liner layer forming an adhesion promoting diffusion barrier may be disposed between the insulation layer and the metal layer. The liner layer can comprise tantalum/tantalum nitride (Ta/TaN), and can have a thickness of about 5-200 nm (0.005-0.2 micron).
The invention will be more readily understood from the following detailed description taken with the accompanying drawings and claims.
Braden Stanton
Infineon Technologies North America Corp.
Powell William
LandOfFree
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