Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – For liquid etchant
Reexamination Certificate
2000-10-16
2003-04-29
Mills, Gregory (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
For liquid etchant
C451S444000
Reexamination Certificate
active
06554951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure relates to integrated circuit fabrication, and more particularly to a system and method for conditioning a polishing pad used in a chemical-mechanical polishing process.
2. Description of the Related Art
Modern integrated circuits (ICs) employ advanced transistor isolation and multi-level interconnect techniques to increase both circuit functionality and processing speed. Conventional transistor isolation fabrication techniques utilizing LOCOS (LOcal Oxidation of Silicon) have been virtually superceded by STI (Shallow Trench Isolation) technology to overcome the “bird's beak” effect associated with LOCOS processing and allows for increased device packing densities. Multi-layer interconnects are pervasively used to facilitate interconnect routing between the transistors of the IC devices, also enabling increased packing densities. In addition, copper interconnects are being implemented in place of conventional aluminum interconnects, due to their improved conductivity and resistance to electromigration over aluminum, to reduce interconnect routing delays and thereby improve processing speed.
STI processing involves the formation of trenches recessed into a semiconductor substrate between adjacent active regions of the IC device. The trenches are then filled in with a dielectric material and subsequently planarized so that the uppermost surfaces of the dielectric and the substrate are approximately equal. Common dielectric materials include oxides, nitrides, or oxynitrides. Interconnect processing involves the formation of an interlevel dielectric between a lower level and an upper level. Contact areas, or vias, are then opened through the interlevel dielectric and subsequently filled in with a conductive material to electrically link the two levels together in the desired interconnect routing scheme. For metallization technologies using inlaid techniques, such as copper interconnects, the metal layers are also created by forming trenches into the interlevel dielectric and filling in the trenches with a conductive material. Additional levels of interconnects may be constructed in the same manner upon the prior levels to form a multi-level interconnect IC device. The interlevel dielectrics are frequently planarized prior to formation of the vias or trenches to minimize elevational disparity across the semiconductor substrate. This facilitates both photolithography of the vias and trenches and provides optimum step coverage of the conductive material being filled in. The conductive layers may also be planarized to form the final interconnect structures.
Modern IC devices simultaneously employ the use of STI and multi-level interconnect technologies to meet the demands for increased functionality and faster processing speeds. Accordingly, planarization of the interlevel dielectrics, conductive layers, and the trench dielectrics is required for optimum fabrication results. Planarization of these layers may be achieved through chemical-mechanical polishing (CMP) techniques, which has received widespread acceptance in the semiconductor processing industry. Generally speaking, CMP processes may be used to globally planarize and remove surface topography irregularities of a material layer(s) through chemical reaction and mechanical abrasion. A typical CMP process involves placing a semiconductor substrate face-down on a polishing pad which is attached to a rotatable table, or platen. An abrasive fluid, known as slurry, is introduced onto the surface of the rotating polishing pad and the substrate is then pressed against the polishing surface by a downward force. The substrate may also be rotated in conjunction with the rotating polishing pad. The chemical-mechanical interaction is provided by solution chemistry and abrasives contained in the slurry. Typical abrasives used by CMP processes include silica, alumina, and ceria. Other abrasives may be utilized and are often matched with the material layer(s) to be removed. Chemical interaction between the slurry and the material layer(s) being polished initiates the polishing process. The abrasives, coupled with the rotational movement of the polishing pad, physically strip the reacted surface material from the substrate. The process continues until the desired thickness amount of the material layer(s) is removed. Upon completion of the polishing process, the substrate is then subjected to a cleaning process to remove residual slurry and foreign particulates, including polish by-products, that may remain on the substrate surface.
By semiconductor fabrication standards, CMP is inherently a dirty process. The use of slurry to facilitate removal of the material layer introduces a significant amount of particles to the substrate surface, which must be removed in the subsequent cleaning step. In addition, during planarization by a CMP process, the substrate surface may be subjected to extremely high local mechanical pressures and exposed to either highly acidic or caustic solutions. Therefore, a substrate planarized by CMP may result in many unwanted defects on or within the upper surfaces. These defects may include, for example, residual particles from the slurry or the abraded substrate surface, chemical contamination from the slurry and/or other fluids, and physical surface damage such as microscratches or film fractures from the mechanical force being applied during polish. These defects have the potential to become yield-limiting defects, affecting die yields of the finished IC devices. For example, microscratches may scratch the surfaces of active regions thereby resulting in higher transistor leakage currents due to crystallographic damages. In addition, a microscratch formed in the surface of the dielectric layer may result in a residual conductive material being trapped into the divots formed by the microscratches during CMP, and potentially short out desired interconnect features. Moreover, residual surface particles may affect areas on the substrate where subsequent photolithography processes occur. The presence of the particles may prevent proper formation of the features defined by the photolithography process. As a result, efforts to substantially reduce the defects introduced by CMP have received considerable awareness.
Efforts to remove residual particles from the polish due to CMP processing have included scrubbing the substrate with brushes, spraying the substrate surface with a pressurized flow of cleaning liquids, and acoustically removing the particles through ultrasonic or megasonic cleaning techniques. Reduction of microscratches have examined minimizing the down force applied to the substrate onto the polishing pad, employing slurries with smaller abrasive grain sizes, and reducing the abrasiveness of the polishing pad. Varying degrees of effectiveness have been gained by these described methods.
Despite the above-described efforts, CMP-induced defects may still be formed and potentially impact final device yields. Considering that CMP processes account for an increasing portion of the entire IC fabrication process flow (STI, local interconnect, inlaid vias and metal), the compounding rate of defects introduced by CMP processes may significantly influence final yields of the IC devices. It would therefore be desirable to provide a method and system for minimizing defects associated with CMW processes. A reduction in defect density of CMP-induced defects may translate into increased die yields of the IC devices being fabricated.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by a CMP pad conditioning system and method in which a chemical reagent may be introduced onto the polishing pad during conditioning of the polishing pad. In addition, the chemical reagent may further be introduced onto a storage apparatus that may be used to store the conditioning device and may further be introduced onto the conditioning surface of the conditioning device which is in abrasive contact with the polishing pad during pad condition
Kaiser John A.
Page Cary R.
Saenz Moses R.
Advanced Micro Devices , Inc.
Kowert Robert C.
MacArthur Sylvia R.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Mills Gregory
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