Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
1997-11-24
2002-03-26
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S690000, C438S691000, C438S692000, C438S693000
Reexamination Certificate
active
06362101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to planarizing surfaces during the formation of integrated circuit devices. More particularly, the present invention relates to improved methods for carrying out chemical mechanical polishing (CMP).
2. Description of the Related Art
During the fabrication of integrated circuit devices, it is often necessary to remove material from the surface of the device at one or more stages of the fabrication process and to planarize material layers before proceeding with further processing steps. With increasing frequency, material removal and planarization are accomplished using chemical mechanical polishing (CMP). CMP processes are carried out by holding a wafer against a rotating polishing surface with a controlled pressure in the presence of a slurry. The slurry often includes both a chemically active component such as an acid or base and a mechanically active, abrasive component such as fine particles of silicon oxide. Though the exact mechanisms are poorly understood, chemical reactions and mechanical abrasion contribute to the polishing and planarization process. CMP methods have been developed for planarizing both metal layers and dielectric layers.
CMP processes may be used for polishing multiple layers in an integrated circuit device. For example, devices such as FETs, diodes or transistors are formed in and on a substrate and then a first level of insulating material is deposited over the integrated circuit device. A pattern of contact holes or vias is defined through the first level of insulating material and, at some point in the process, the vias are filled with a conducting material to define vertical interconnects through the first level of insulating material to contact appropriate portions of the devices on the surface of the substrate. Because certain wiring line metals such as aluminum do not provide adequate fill within the vias, and it is common to fill the vias with tungsten deposited using chemical vapor deposition (CVD). Depositing CVD tungsten into the via results in a layer of tungsten being formed over the insulating material as well as within the via through the insulating material. After the via is filled, the layer of tungsten that overfilled the via is removed and an aluminum wiring line is deposited over the dielectric layer and over the via. The layer of tungsten may be removed using an etch back step such as reactive ion etching (RIE). The RIE step, however, can overetch the tungsten and remove tungsten from within the via. This can result in poor contact between the recessed tungsten within the via and the subsequently deposited aluminum wiring line layer. Moreover, particles remaining on silicon wafer surface after tungsten etch back will be a killer of device. As an alternative to performing an etch back step, CMP processes can be used for removing excess tungsten.
For tungsten CMP, a two step process is conventionally used. In the first step, the wafer is polished at a first polishing station using a slurry having an oxidizer and a low pH to remove the excess tungsten layer from the surface of the insulating layer. The underlying insulating layer may be used as an etch stop during the first CMP step. In the second step, the wafer is moved to a second polishing station in which a high pH slurry is used to planarize and polish the insulating layer. Both steps are conventionally believed necessary because the first polishing step leaves scratches in the insulating layer which can trap contaminants and subsequently cause shorts between conductive structures. The second polishing step is used to buff the scratches out of the insulating layer. Ideally, the second polishing step is carried out so that the thickness of the removed oxide layer during the second polishing step equals the depth of the largest scratch resulting from the first metal removal step. In addition to scratches, the first polishing step may also remove a portion of the tungsten from within the via because the slurry is formulated to remove the tungsten at a greater rate than the dielectric material. The second step of polishing the dielectric layer with a slurry that is selective to the dielectric layer acts to planarize the dielectric layer and the tungsten within the via.
FIG. 1
illustrates a conventional CMP set-up. A wafer
10
is mounted to a wafer carrier
12
above a rotating platen
14
. The wafer carrier
12
can exert a force on the wafer
10
and is attached to a rotating spindle
20
so that the wafer can be rotated independently of the platen
14
. Polishing pad
16
is disposed on the platen
14
and polishing slurry
18
is supplied to the surface of the rotating pad. As illustrated in
FIG. 2
, the wafer carrier may include a chuck
22
and backing film
24
. The backing film
24
is placed between the wafer
10
and the chuck
22
to provide the desired level of elasticity between the chuck
22
and the wafer
10
. If the wafer
10
is held too tightly to the chuck
22
, then any particles or non-planar defects in the chuck
22
will be transmitted to the wafer
10
and cause a thin spot or defect within the wafer
10
. One or more polishing pads
16
may be used in order to provide the desired level of elasticity between the wafer
10
and the platen
14
. If the contact between the polishing pad and the wafer is too rigid, there is an increased risk of wafer breakage. If the polishing pad
16
is too soft, then it will deform into areas on the wafer
10
that are not intended to be polished and uneven amounts of material will be removed from the surface of the wafer. The resultant structure will have a less planar surface than desired. The polishing pad is usually kept somewhat rough, with protrusions of about 1 to 10 &mgr;m built into the pad to hold and transport the polishing slurry.
The exact mechanisms by which chemical mechanical planarization takes place are complex and poorly understood. There are numerous variables related to both the chemical and mechanical aspects of CMP. Chemistry-related factors include the slurry type, slurry pH, slurry solid content, slurry flow, and process temperature. Mechanical-related factors include polishing pressure, back pressure, platen speed, and pad type. The slurry mixture is typically either an acid or base along with an abrasive material such as silicon oxide. For polishing and removing a metal layer such as tungsten, it is conventional to use a slurry solution having an oxidizing component such as H
2
O
2
and a pH of 2 to 4 in the first step of tungsten CMP. For polishing or planarizing an oxide layer in the second step of tungsten CMP, it is conventional to use an alkali based solution such as KOH with a pH of 10 to 11.5. For uniform polishing it is generally desirable for: (1) each point on the wafer to travel the same velocity relative to the polishing pad; (2) the polishing slurry to be uniformly distributed under the wafer; and (3) the wafer to be symmetrical.
The two steps of the process for removing the excess tungsten and buffing the underlying insulating layer are generally carried out at different polishing stations, or by switching the polishing pad between the first and second CMP steps. Because of differences between the first and second slurries used for polishing the metal and the insulator, the same pad is not used for the first and second CMP steps. If the same pad were used, problems due to pH shock and particle generation will occur because acid-base reactions take place between the first acidic slurry and the second basic slurry and precipitate undesirable particles on the pad. The need for a two step process causes the tungsten CMP process to be more time consuming, expensive and unpredictable than desired.
SUMMARY OF THE PREFERRED EMBODIMENTS
It is an object of the present invention to provide a simplified tungsten CMP process where, through appropriate control of selected process variables, tungsten CMP can be acceptably performed using a single polishing pad or at a single polishing station.
Embodiments of the p
Lur Water
Sun Shih-Wei
Wu Juan-Yuan
Yang Ming-Sheng
Perez-Ramos Vanessa
Rabin & Berdo
United Microelectronics Corp.
Utech Benjamin L.
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