Abrasive tool making process – material – or composition – With inorganic material – Metal or metal oxide
Reexamination Certificate
1999-02-26
2001-05-22
Marcheschi, Michael (Department: 1755)
Abrasive tool making process, material, or composition
With inorganic material
Metal or metal oxide
C106S003000, C438S692000, C438S693000
Reexamination Certificate
active
06235071
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of polishing a metal interconnection layer, and more particularly to a chemical mechanical polishing method for obtaining highly accurate in-plane uniformity in polishing rate of a semiconductor wafer surface including buried metal interconnections such as copper interconnections.
A conventional method of forming a buried metal interconnection in a semiconductor wafer will be described with reference to
FIGS. 1A through 1E
.
With reference to
FIG. 1A
, an insulation layer
102
with an active region is formed on a semiconductor substrate
101
.
With reference to
FIG. 1B
, a photo-resist pattern
105
is formed on the insulation layer
102
. Thereafter, dry etching of the insulation layer
102
is carried out using the photo-resist pattern
105
as a mask thereby to form a contact hole
106
in the insulation layer
102
so that the contact hole
106
is positioned over the active region of the semiconductor substrate
101
. A part of the active region of the semiconductor substrate
101
is thus shown through the contact hole
106
. Thereafter, the used photo-resist pattern
105
is removed from the surface of the insulation layer
102
.
With reference to
FIG. 1C
, a barrier layer
103
made of a metal such as Ti or Ta is formed covering the top surface of the insulation layer
102
as well as on side walls and a bottom of the contact hole
106
so that the barrier layer
103
is in contact with the part of the active region of the semiconductor substrate
101
.
With reference to
FIG. 1D
, a conductive material
104
is deposited covering the barrier layer
103
so that the contact hole
106
is completely filled with the conductive material
104
and the conductive material
104
extends over the barrier layer
103
on the top surface of the conductive material
104
.
With reference to
FIG. 1E
, a chemical mechanical polishing method is carried out to polish the surface of the conductive material
104
so that the conductive material
104
extending over the insulation layer
102
is removed whereby the conductive material
104
remains only within the contact hole
106
. The chemical mechanical polishing is carried out by use of a chemical mechanical polishing apparatus which has a rotatable polishing plate
107
affixed with a polishing cloth. The wafer is fixed to a wafer carrier. The rotatable polishing plate
107
is made to rotate and brought into contact with the wafer surface so that the conductive material
104
is polished with the polishing cloth affixed on the rotating polishing plate
107
, wherein a polishing slurry containing polishing particles such as alumina or silica particles and an etchant such as hydrogen peroxide are supplied onto the exposed surface of the conductive material
104
on the wafer.
The improvements of the chemical mechanical polishing method have taken into two distinct directions. The first one is to improve the compositions of the polishing agent used for the chemical mechanical polishing method. The second one is to improve the surface of the wafer being polished by the chemical mechanical polishing method.
Japanese laid-open patent publication No. 7-94455 addresses the improvement in the composition of the polishing agent, wherein it is suggested to use as an etchant, a hydrochloric acid solution, an ammonium persulfate solution, a chromium oxide solution, a phosphoric acid solution, an ammonium hydroxide solution, a solution containing both ammonium copper chloride and ammonium hydroxide, and a solution containing both ammonium and hydrogen peroxide as well as a mixture of those solutions. Those etchants provide effects of increase in polishing rate ratio of a metal layer to an insulation layer, so that the function of the insulation layer as a polishing stopper is enhanced, whereby the progress of polishing the metal layer extending both over the top surface of the insulation layer and within the through hole or groove in the insulation layer is stopped just when the top surface of the insulation layer is exposed. This makes it possible to achieve exact control in thickness of the metal interconnection. This conventional polishing method uses silicon dioxide particles having diameters of not larger than 0.1 micrometer as polishing particles. The hardness of the silicon dioxide particles is lower than alumina particles. Further, the silicon dioxide particles are fine particles. For those reasons, those silicon dioxide polishing particles are capable of polishing a soft metal layer such as a copper layer without scratching the soft metal layer, thereby resulting in no deterioration in characteristics of the soft metal interconnection.
The above first conventional polishing method is, however, plagued with a problem that a center region of the soft metal interconnection is over-etched by the etchant, whilst the top surface of the insulation layer is not etched due to the polishing stopper effect of the insulation layer.
The present inventors previously have proposed to improve the polishing surface structure to be polished by the chemical mechanical polishing method in order to solve the above problem. This second conventional chemical mechanical polishing method is disclosed in Japanese laid-open patent publication No. 9-148431. A through hole or a groove is formed in an insulation layer overlying a semiconductor substrate. A conductive layer is then formed which extends both over a top surface of the insulation layer and within the through hole or the groove. Further, a passivation layer is formed over the conductive layer. The passivation layer and the conductive layer are concurrently polished by the chemical mechanical polishing method so that the conductive layer remains only within the through hole or the groove in the insulation layer. Example 3 of the above Japanese publication provides the following descriptions. A via hole and an interconnection groove are formed in an insulation layer overlying a semiconductor substrate. A Ti/TiN barrier layer is entirely deposited by a sputtering method so that the Ti/TiN barrier layer covers both the top surface of the insulation layer and vertical side walls and bottoms of the via hole and the groove. A first copper interconnection layer is deposited on the Ti/TiN barrier layer by a chemical vapor deposition method, wherein the first copper interconnection layer has a thickness of one-third of a minimum diameter of the via hole formed in the insulation layer. A first passivation Ti layer having a thickness of 0.1 micrometers is then deposited on the first copper interconnection layer by a chemical vapor deposition method. A second copper interconnection layer is deposited on the first passivation Ti layer by a chemical vapor deposition method, wherein the second copper interconnection layer has a thickness of one-third of a maximum width of the groove formed in the insulation layer. A second passivation Ti layer having a thickness of 0.1 micrometers is then deposited on the second copper interconnection layer by a chemical vapor deposition method. The laminations of the Ti/TiN barrier layer, the first copper interconnection layer, the first passivation layer, the second copper interconnection layer and the second passivation layer are polished by a chemical mechanical polishing method by use of a polishing agent where a solid component concentration of alumina polishing particles is 12% and a ratio of water to hydrogen peroxide is 1:1, so that the laminations remain only within the via hole and the groove in the insulation layer. An acceptable solid component concentration of alumina polishing particles is in the range of 5%-33% and an acceptable ratio of water to hydrogen peroxide is in the range of 1:0.1 to 1:2.
The above second conventional chemical mechanical polishing method is effective to avoid any over-etching of the center portion of the interconnection in the groove or the contact in the via hole for the purpose of formation of no void in a center portion of the interconnection layer or in a center por
Suzuki Mieko
Tsuchiya Yasuaki
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
Marcheschi Michael
NEC Corporation
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