Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2006-05-02
2006-05-02
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S427000, C438S462000, C438S690000
Reexamination Certificate
active
07037802
ABSTRACT:
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
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Liu, George Y., Zhang, Ray F., HSU, Kelvin, Camilletti, Lawrence, Chip-Level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films, CMP Technology, Inc., and Rockwell Semiconductor, pp. 8, NO Date.
Lur Water
Wu Juan-Yuan
Yang Ming-Sheng
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
Picardat Kevin M.
United Microelectronics Corporation
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