Chemical mechanical polishing in forming semiconductor device

Details Chemical mechanical polishing in forming semiconductor device Chemical mechanical polishing in forming semiconductor device

2002-11-13

2004-09-14

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S424000, C438S427000, C438S692000

Reexamination Certificate

active

06790742

ABSTRACT:

BACKGROUND
1. Field of Invention
This invention relates to a chemical mechanical polishing (CMP) applied in forming shallow trench isolation (STI), and more particularly, to a process of forming a STI structure combining CMP, using a partial reverse active mask.
2. Background
CMP is a technique ideal for applying in global planarization in very large scale integration (VLSI) and even in ultra large-scale integration (ULSI). Moreover, CMP is likely to be the only reliable technique as the feature size of the integrated circuit (IC) is highly reduced. Therefore, it is of great interest to develop and improve CMP techniques to reduce costs.
As the IC devices are continuously sized down to a linewith of 0.25 &mgr;m or even 0.18 &mgr;m (deep sub-half micron), using CMP to planarize the wafer surface, especially to planarize the oxide layer on the surface of the shallow trench, becomes even more important. To prevent the dishing effect occurring at the surface of a larger trench during CMP process and to obtain a superior CMP uniformity, a reverse tone active mask was proposed, in cooperation with an etching back process.
Typically, the active regions have varied sizes and the shallow trenches between the active regions also have different sizes.
FIGS. 1A
to
1
E are cross sectional views showing the process steps for forming shallow trench isolation, using CMP. Referring to
FIG. 1A
, on a substrate
10
, a pad oxide
15
and a silicon nitride layer
16
are deposited successively. By photolithography, the substrate
10
, the pad oxide layer
15
and the silicon nitride layer
16
are anisotropically etched to form shallow trenches
14
a
,
14
b
,
14
c
and define active regions
12
a
,
12
b
,
12
c
,
12
d
. The sizes of the shallow trenches
14
a
,
14
b
,
14
c
are different since the sizes of the active regions
12
a
,
12
b
,
12
c
,
12
d
are varied.
Next, referring to
FIG. 1B
, an oxide layer
18
is deposited by atmosphere pressure chemical vapor deposition (APCVD) on a substrate
10
to fill the interior of the shallow trenches
14
a
,
14
b
,
14
c
. However, due to the step coverage of the oxide layer
18
, the deposited oxide layer
18
has an uneven surface and a rounded shape. Then, a photoresist layer is coated on the surface of the oxide layer
18
and patterned to form a reverse active mask
20
by photolithography. The reverse active mask
20
covers the shallow trenches
14
a
,
14
b
,
14
c
and is complementary to the active regions
12
a
,
12
b
,
12
c
,
12
d
. However, during the formation of the reverse active mask, misalignment causes the oxide layer
18
to cover more than the shallow trenches
14
a
,
14
b
,
14
c.
Referring to
FIG. 1C
, the oxide layer
18
exposed outside the reverse active mask
20
is etched until the silicon nitride layer
16
is exposed so that only a part of the silicon oxide layer
18
, the silicon oxide layer
18
a
, is formed. After removing the reverse active mask
20
, as shown in
FIG. 1D
, it is observable that the silicon oxide layer
18
a
remained does not fully cover the shallow trenches
14
a
,
14
b
,
14
c
at one sides of the shallow trenches
14
a
,
14
b
,
14
c
, therefore, forming cavities
22
, but at the other sides over-cover the shallow trenches
14
a
,
14
b
,
14
c
, forming photo-overlap
24
.
Referring to
FIG. 1E
, the portion of the oxide layer
18
a
higher than the shallow trenches
14
a
,
14
b
,
14
c
is polished by CMP until the surface of the silicon nitride layer
16
is exposed. Therefore, the silicon nitride layer
16
and the silicon oxide layer
18
a
are at the same level. The profile of the silicon oxide layer
18
a
formed by APCVD is rather rounded and the APCVD silicon oxide layer
18
a
is hard to planarize. Moreover, it is obvious that the silicon oxide layer
18
a
does not fully fill the shallow trenches
14
a
,
14
b
,
14
c
but forms the concaves
22
. The undesired concaves
22
may cause kink effect and consequent short circuit or leakage current which therefore influence the yield.
As a result, it is important to overcome the problems coming after the formation of the concaves due to the misalignment of the reverse active mask during the process of CMP, especially, while nowadays the linewidth is decreasing.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
In one aspect, the invention provides a method of chemical-mechanical polishing for forming a shallow trench isolation, wherein a substrate having a plurality of active regions, including a plurality of relatively large active regions and a plurality of relatively small active regions and an alignment mark. The method comprises: forming a plurality of shallow trenches between the active regions; forming an oxide layer over the substrate, so that the shallow trenches and the alignment mark are filled therewith; forming a partial reverse active mask on the oxide layer, wherein the partial reverse active mask has an opening at each relatively large active region and at the alignment mark when the reverse active mask completely covers each relatively small active region and trenches, wherein the opening exposes a portion of the oxide layer; removing portions of the oxide layer on each large active region and at the alignment mark; removing the partial reverse active mask; and planarizing the oxide layer.
In another aspect, the invention provides a method of chemical-mechanical polishing in forming a multi-layered semiconductor device comprising a substrate. The method comprises forming an alignment mark in the substrate and a plurality of shallow trenches between active regions of the semiconductor substrate; forming an oxide layer over the substrate; forming a partial reverse active mask on the oxide layer, wherein the partial reverse active mask has an opening over a portion of at least one active region and over the alignment mark; removing portions of the oxide layer over at least one active region and over portions of the alignment mark to expose a portion of the oxide layer; removing the partial reverse active mask; and planarizing the oxide layer.
In yet another aspect, the invention provides a method of forming a semiconductor device having an alignment mark. The method comprises forming an alignment mark in a substrate; forming at least one active area on the substrate; forming an oxide layer over the substrate, wherein the oxide layer covers at least a portion of the alignment mark; forming a partial reverse active mask on the oxide layer, wherein the partial reverse active mask has an opening over at least a portion of the alignment mark; removing portions of the oxide layer to expose a portion of the oxide layer; removing the partial reverse active mask; and planarizing the oxide layer.


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