Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-03-28
2006-03-28
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S500000, C438S778000, C438S791000, C438S942000
Reexamination Certificate
active
07018906
ABSTRACT:
A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
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Liu, George Y., Zhang, Ray F., Hsu, Kelvin, Camilletti, Lawrence, Chip-Level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films, CMP Technology. Inc., and Rockwell Semiconductor, pp. 8, No Date.
Chen Coming
Lur Water
Wu Juan-Yuan
Meza Peter J.
Picardat Kevin M.
United Microelectronics Corporation
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