Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-09-08
2000-04-25
Fahmy, Wael
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438359, 438426, 438427, H01L 2176
Patent
active
060543647
ABSTRACT:
The present invention is directed to am improved chemical mechanical polish etch stop for a trench isolation and a method for making same. The method comprises forming at least four process layers above a surface of a semiconducting substrate. The method further comprises patterning said plurality of process layers to define an opening exposing a portion of the surface of the substrate. A trench is formed in the substrate, and the trench and the opening are then filled with a dielectric material. The surface of the dielectric material and the surface of the top process layer are then planarized. The present inventive structure is comprised of at least four process layers positioned above a substrate, an opening formed in said plurality of layers, a trench formed in said substrate, and a dielectric material positioned in said opening and said.
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Silicon Processing for the VLSI Era, vol. 2: Process Integration, by Stanley Wolf Ph.D., 1990, pp. 51-52.
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices
Fahmy Wael
Pham Long
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