Chemical mechanical polishing composition and process

Details Chemical mechanical polishing composition and process Chemical mechanical polishing composition and process

1998-03-23

2000-09-12

Koslow, C. Melissa

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438692, 216 89, 106 3, 51307, 51308, 51309, C09K 1300

Patent

active

061177830

DESCRIPTION:

BRIEF SUMMARY
INTRODUCTION

1. Technical Field
This invention relates to an improved composition and process for the chemical mechanical polishing or planarization of semiconductor wafers. More particularly, it relates to such a composition and process which are tailored to meet more stringent requirements of advanced integrated circuit fabrication.
2. Background
Chemical mechanical polishing (or planarization) (CMP) is a rapidly growing segment of the semiconductor industry. CMP provides global planarization on the wafer surface (millimeters in area instead of the usual nanometer dimensions). This planarity improves the coverage of the wafer with dielectric (insulators) and metal substrates and increases lithography, etching and deposition process latitudes. Numerous equipment companies and consumables producers (slurries, polishing pads, etc.) are entering the market.
CMP has been evolving for the last ten years and has been adapted for the planarization of inter-layer dielectrics (ILD) and for multilayered metal (MLM) structures. During the 80's, IBM developed the fundamentals for the CMP process. Previously (and still used in many fabs today) plasma etching or reactive ion etching (RIE), SOG ("spin on glass"), or reflow, e.g., with boron phosphorous spin on glass (BPSG), were the only methods for achieving some type of local planarization. Global planarization deals with the entire chip while "local" planarization normally only covers a .about.50 micron.sup.2 area.
At the 1991 VMIC Conference in Santa Clara, Calif., IBM presented the first data about CMP processes. In 1993 at the VMIC Conference, IBM showed that a copper damascene (laying metal lines in an insulator trench) process was feasible for the MLM requirements with CMP processing steps. In 1995 the first tungsten polishing slurry was commercialized.
The National Technology Roadmap for the Semiconductor Industries (1994) indicates that the current computer chips with 0.35 micron feature sizes will be reduced to 0.18 micron feature size in 2001. The DRAM chip will have a memory of 1 gigabit, and a typical CPU will have 13 million transistors/cm.sup.2 (currently they only contain 4 million). The number of metal layers (the "wires") will increase from the current 2-3 to 5-6 and the operating frequency, which is currently 200 MHz, will increase to 500 MHz. This will increase the need for a three dimensional construction on the wafer chip to reduce delays of the electrical signals. Currently there are about 840 meters of "wires"/chip, but by 2001 (without any significant design changes) a typical chip would have 10,000 meters. This length of wire would severely compromise the chip's speed performance.
The global planarization required for today's wafer CDs (critical dimensions) improves the depth of focus, resulting in better thin metal film deposition and step coverage and subsequently increases wafer yields and lowers the cost/device. It is currently estimated (1996) that it costs $ .about.114/layer/wafer with current limited planarization processes. As the geometries become smaller than 0.35 micron, the planarity requirements for better lithography become critical. CMP is becoming important, if not essential, for multiple metal levels and damascene processes.
The CMP process would appear to be the simple rotation of a wafer on a rotary platen in the presence of a polishing medium and a polishing pad that grinds (chips away) the surface material. The CMP process is actually considered to be a two part mechanism: step one consists of chemically modifying the surface of the material and then in the final step the altered material is removed by mechanical grinding. The challenge of the process is to control the chemical attack of the substrate and the rate of the grinding and yet maintain a high selectivity (preference) for removing the offending wafer features without significant damage to the desired features. The CMP process is very much like a controlled corrosion process.
An added complexity is that the wafer is actually a complex sandwich of materials with w

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