Chemical mechanical polishing composition and method of...

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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C051S307000, C051S308000, C051S309000, C106S003000, C252S079400

Reexamination Certificate

active

06599837

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the chemical mechanical planarization (CMP) of semiconductor wafers and more specifically to CMP polishing slurries for polishing metal layers such as copper layers on semiconductor wafers.
BACKGROUND OF THE INVENTION
Integrated circuits are chemically and physically integrated into a substrate such as a silicon or gallium arsenide wafer by patterning layers on a substrate. In particular, semiconductors are formed by providing tungsten or copper wiring or metallization in discrete layers of dielectric films to form a multilayer structure. The metallization is adhered to the dielectric film through a thin liner film comprising tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN). The metallization layer and the liner film are deposited on a patterned dielectric film and then polished, typically by chemical-mechanical planarization (CMP), to expose the dielectric layer.
The chemical mechanical planarization (CMP) process is a well-known technique in the semiconductor manufacturing industry. In a typical CMP process, the surface of the semiconductor material to be polished is held against a polishing pad at a predetermined pressure while the polishing pad rotates at a predetermined angular speed. The wafer may also rotate. A polishing slurry is supplied to the interface between the polishing pad and the semiconductor material surface to be polished. The polishing slurry is an aqueous solution of an oxidizing agent at a specific pH for chemically transforming the surface of the semiconductor material by oxidation. In addition, abrasive particles such as alumina, silica, or ceria particles for mechanical polishing are also included in the polishing slurry. Thus, a typical CMP process includes chemically transforming the metal layer using an oxidizing agent and mechanically polishing the metal layer using abrasive particles as well as the friction force exerted by the polishing pad on the wafer surface.
One problem with chemical mechanical polishing is that the metallization layer (e.g. copper or tungsten) generally polishes at a different rate than the underlying liner film thereby resulting in uneven planarization. This uneven planarization is generally in the form of overpolishing (dishing) and dielectric erosion. This is particularly true when the metal layer being polished is copper because copper is typically softer and polishes at a faster rate than the metals (e.g. tantalum and tantalum nitride) used in the liner film. Because the faster copper polishing rate can result in overpolishing, a corrosion inhibitor such as benzotriazole (BTA) may be included in the polishing slurry to slow down the rate of copper removal in the lines and vias. However, the presence of a corrosion inhibitor in the slurry also results in a decrease in the rate of planarization and the production of integrated circuits at a slower rate.
One method of overcoming the reduction rate caused by the presence of the corrosion inhibitor and thus increasing the copper polishing rate has been to modify the mechanical polishing parameters in the chemical mechanical planarization process (e.g. carrier rotation, platen rotation, downforce, and backforce). However, increasing the polishing rate by mechanical means results in a process that is difficult to control. As a result, although the polishing rate increases, the polished surface does not possess the desired level of planarity. Specifically, the rate of mechanical removal disadvantageously overcomes the rate of chemical removal resulting in a non-planar polished surface.
As is well understood in the art, the formation of planar layers in the formation of integrated circuits is essential to the operation of these integrated circuits. Therefore, there is a need in the art for a method of polishing metal layers such as copper layers for integrated circuits that provides good planarization without dishing or dielectric erosion. Furthermore, there is a need in the art to increase the rate of metal CMP polishing and particularly copper CMP polishing that does not negatively affect the planarization of the metal layers.
SUMMARY OF THE INVENTION
The present invention provides a chemical mechanical planarization (CMP) polishing composition that produces good planarization of metal layers and particularly copper layers with limited dishing and dielectric erosion. In addition, the CMP polishing composition of the present invention polishes the metal layers at a fast rate that can be easily controlled. Therefore, the present invention produces good quality integrated circuits at a faster rate than prior art processes.
The CMP polishing composition of the present invention provides a combination of a triazole or a triazole derivative and a ferricyanide salt at a pH of between about 1 and about 6 to produce the above benefits. In particular, the present composition includes a plurality of abrasive particles, a triazole or a triazole derivative, a ferricyanide salt oxidizing agent and water and has a pH of from about 3 to about 5. The abrasive particles for use in the invention can be alumina, silica or ceria particles or other particles suitable for CMP polishing. The triazole or triazole derivative is preferably benzotriazole (BTA) and is present in a corrosion-inhibiting effective amount, preferably from 0.05 to 2M. The ferricyanide salt oxidizing agent is preferably potassium ferricyanide (K
3
Fe(CN)
6
) and is present in an oxidizing effective amount, preferably from 0.05 to 2M. The pH of from about 1 to about 6, and preferably between about 3 and about 5, can be produced merely by the addition of the above listed components or buffers can be added to the composition to provide the desired pH.
In addition to the present composition, the invention includes a method for polishing a metallization layer on a semiconductor substrate. In particular, the method comprises removing at least a portion of a metallization layer on a semiconductor wafer by polishing the metallization layer using the CMP polishing composition described above. Preferably, the metallization layer polished in accordance with the invention comprises copper.


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