Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-10-18
2003-10-28
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S693000
Reexamination Certificate
active
06638866
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of forming shallow trench isolation in the fabrication of integrated circuits, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is desirable for improved planarity over other isolation techniques. Chemical-mechanical polishing (CMP) processes are key to forming STI regions. However, a reverse mask is often needed to form STI due to low CMP selectivity for oxide to nitride and the dishing effect at wide field regions. Therefore, to overcome these problems, a slurry having a high selectivity of oxide to nitride and high planarity is needed. Furthermore, a high selectivity CMP process can induce macro or micro-scratches. Thus, reducing scratches is also an important topic. Another issue for STI CMP is pattern density effect. This will result in a large variation in trench oxide thickness after CMP which leads to difficulties in controlling polysilicon photolithography and etching. It is desired to find a process to resolve all of these critical issues.
U.S. Pat. 6,043,133 to Jang et al shows a CMP STI process with reverse mask. U.S. Pat. No. 6,107,159 to Chuang, U.S. Pat. No. 5,837,612 to Ajuria, U.S. Pat. No. 5,950,093 to Wei, and U.S. Pat. No. 5,889,335 to Kuroi et al show other STI processes.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming shallow trench isolation device in the fabrication of an integrated circuit.
Another object of the present invention is to provide an effective and very manufacturable method of forming shallow trench isolation using chemical mechanical polishing (CMP) wherein a low pattern-density effect is achieved.
Another object of the present invention is to form shallow trench isolation using CMP wherein there is minimal trench oxide thickness variation.
A further object of the invention is to form shallow trench isolation using CMP to achieve direct and low-defect CMP process.
A still further object is to form shallow trench isolation using CMP wherein subsequent polysilicon photolithography and etching difficulties are minimized.
In accordance with the objects of this invention a new method of forming shallow trench isolation using CMP is achieved. A pad oxide layer is grown overlying a silicon semiconductor substrate. A polysilicon layer is: deposited overlying the pad oxide layer. A nitride layer is deposited overlying the polysilicon layer. Trenches are etched through the nitride layer, polysilicon layer, and pad oxide layer into the silicon semiconductor substrate. The trenches are filled with an oxide layer wherein the oxide layer extends above a top surface of the nitride layer. In one alternative, a silicon oxynitride layer is deposited overlying the oxide layer. A first polishing is performed to polish away the silicon oxynitride layer and oxide layer using a first slurry having high selectivity of oxide to nitride. A second polishing is performed to polish away the oxide layer using a second slurry having a low selectivity of oxide to nitride and having low-defect properties. The silicon nitride layer is removed, and a third high-selectivity slurry is used to planarize the oxide layer to the polysilicon surface to complete formation of shallow trench isolations. In a second alternative, the oxide layer is etched away except where it overlies the trench areas. Then, a first polishing is performed to polish away the oxide layer using a first slurry having a low selectivity of oxide to nitride and having low-defect properties. The nitride layer is removed and then a second polishing is performed to planarize the oxide layer to the polysilicon layer using a second slurry having high selectivity of oxide to polysilicon to complete formation of shallow trench isolations.
REFERENCES:
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 5930645 (1999-07-01), Lyons et al.
patent: 5950093 (1999-09-01), Wei
patent: 5994201 (1999-11-01), Lee
patent: 6015757 (2000-01-01), Tsai et al.
patent: 6017803 (2000-01-01), Wong
patent: 6043133 (2000-03-01), Jang et al.
patent: 6069081 (2000-05-01), Kelleher et al.
patent: 6107159 (2000-08-01), Chuang
patent: 6165854 (2000-12-01), Wu
patent: 6410403 (2002-06-01), Wu
patent: 6528389 (2003-03-01), Allman et al.
Cheng Juing-Yi
Su Kevin
Ackerman Stephen B.
Chen Kin-Chan
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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