Chemical mechanical planarization of low dielectric constant...

Details Chemical mechanical planarization of low dielectric constant... Chemical mechanical planarization of low dielectric constant...

2000-04-11

2002-07-09

Utech, Benjamin L. (Department: 1765)

Compositions

Etching or brightening compositions

Reexamination Certificate

active

06416685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the chemical mechanical planarization of surfaces. More particularly, the present invention relates to the planarization of relatively soft materials, typically low dielectric constant materials as encountered in the fabrication of integrated circuits.
2. Description of Related Art
Fabrication of integrated circuits (“ICs”) to improve performance and reduce costs involves complex analysis of materials properties, processing technology and IC design. IC's consist of multiple layers of conducting, insulating and semiconductor materials, interconnected in various ways by conducting metallic channels and plugs (“vias”), including various dopants implanted into various materials for producing the electronic functionality desired of the IC. The near-universal trend in the manufacture of integrated circuits is to increase the density of components fabricated onto a given area of wafer, increase the performance and reliability of the ICs, and to manufacture the ICs at lower cost with less waste and fewer defective products generated by the manufacturing process. These goals lead to more stringent geometric and dimensional requirements in the manufacturing process. In particular, etching precise patterns into a layer is facilitated by the layer having a surface as nearly planar as feasible at the start of the patterning process. For the common case of patterning by means of photolithography, a planar surface permits more precise location and dimensioning for focusing the incident radiation onto the surface to be etched than would be possible with a surface having deviations from planarity. Similar conclusions typically apply for electron beam or other means of etching. That is, deviations from planarity of the surface to be etched reduce the ability of the surface to support precisely positioned and precisely dimensioned patterns. In the following description of the present invention we focus on the typical etching, planarization and photolithography processes as practiced in the manufacture of ICs. However, this is by way of illustration and not limitation, as those of ordinary skill in the art of etching will appreciate that the techniques of the present invention producing planar surfaces will have applicability in increasing the precision of etching by means other than photolithography. In addition, the present invention is not limited to the field of IC manufacture and may find applicability in other areas of technology requiring planar surfaces.
Chemical Mechanical Planarization (“CMP”) has been successfully integrated into integrated circuit multilayer manufacturing processes to achieve highly planar surfaces as described in text books (for example, “Microchip Fabrication” by Peter Van Zant, 3rd Ed., 1997) and generally known in the art. We note that “CMP” is also used in the art to denote “Chemical Mechanical Polishing” as well as “Chemical Mechanical Planarization”. We use CMP herein synonymously in either sense without distinction.
A typical CMP process is depicted schematically in FIG.
1
. During a CMP process, the wafer,
1
, is typically held inside a rotating carrier and pressed onto a rotating pad,
2
, under pressure,
6
, while an abrasive slurry,
5
, (typically containing particles of abrasive such as SiO
2
, Al
2
O
3
, and the like) flows between the wafer and the pad. The slurry,
5
, will typically contain reagents for chemically etching the wafer,
1
, leading to chemical as well as mechanical removal of material. Thus, in the typical practice of CMP, material removal is effected by a combination of chemical attack and mechanical abrasion.
Typically, the wafer,
1
, will be caused to rotate as depicted by
4
in
FIG. 1
, while the polishing pad will itself rotate (
3
in FIG.
1
).
FIG. 1
depicts the polishing pad and wafer rotating in the same direction (for example, clockwise when viewed from above as in FIG.
1
). However, this is merely for purposes of illustration and counter-rotation of wafer and polishing pad is also practiced. In addition to the rotation of the wafer depicted by
4
in
FIG. 1
, the wafer,
1
, may be caused to oscillate in the plane of the surface being polished, substantially perpendicular to the direction of the applied force,
6
. Such oscillation is depicted as
7
in FIG.
1
.
The necessary parameters for polishing SiO
2
-based intermetal dielectric layers occurring in ICs have become well known in the semiconductor industry. The chemical and mechanical nature of polishing and wear of these SiO
2
-based dielectric layers (“SiO
2
dielectrics”) have been reasonably well developed. One problem with the SiO
2
dielectrics, however, is that the dielectric constant is relatively high, being approximately 3.9. Thus, to improve the electrical performance of ICs, it would be highly desirable to incorporate a low dielectric constant material into semiconductor structures while still being able to utilize the CMP systems for polishing the surface of the resulting dielectric material during the semiconductor wafer processing.
As the geometry of the integrated circuits continues to shrink, the intrinsic circuit delays will increase due to greater resistance in the metal interconnects and also due to undesired (“parasitic”) capacitance effects arising from the circuit interconnects. Strategies being developed to reduce the parasitic capacitance effects include incorporating metals with lower resistivity values, such as copper, and providing electrical isolation with insulating materials having low dielectric constants relative to the SiO
2
dielectrics.
As described herein, “low dielectric constant materials” may occur in numerous physical and chemical forms, including organic polymer materials, porous dielectric materials, whether organic or inorganic, and mixed organic and inorganic materials, whether porous or not (examples include FLARE, SILK, HOSP, NANOGLASS, ELK, and Polyimides). Typically these low dielectric constant materials are polymer dielectric materials which include unique chemical and mechanical characteristics, including a relatively high concentration of organic materials. However, low dielectric constant materials may also include relatively highly porous materials (typically inorganic) or materials exhibiting a mixture or combination of properties and characteristics (organic, polymeric, porous, inorganic, etc.). The low dielectric constant films can typically be deposited utilizing a variety of techniques including chemical vapor deposition (CVD), physical vapor deposition (PVD) and spin coating. The polymer materials generally are mechanically soft and they readily exhibit plastic deformation and hence they easily can be scratched. In contrast, however, to their mechanical sensitivity, polymers are often chemically inert. The combination of the characteristics of the polymer dielectric materials makes use of a conventional aqueous based CMP process difficult.
Theoretically and practically, use of a hard CMP pad results in better planarity of the polished wafer while use of a soft CMP pad provides better surface qualities and uniformity of the polished films. The current generation of semiconductor devices (which are typically made containing tungsten and oxides) are typically planarized using CMP with an industry standard hard pad, such as the IC® pad, for primary planarization and a standard soft pad, such as the Politex® pad, for secondary buff polishing. However, using the standard IC® pad and the conventional abrasive slurries (SiO
2
, Al
2
O
3
, CeO
2
, and the like) to polish low dielectric constant materials, which typically are much softer than the conventional materials used in integrated circuits, tends to cause significant scratches on the polished surfaces of low dielectric films. Attempts to use soft pads like Polytex® pads to polish these soft materials have shown some success in avoiding severe scratches, but do not efficiently achieve good planarity in reasonable processing times. (S. P. Murkarka and R. Gutmann, 1994 An

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