Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
1998-03-31
2001-02-06
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S023000, C712S210000
Reexamination Certificate
active
06185671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessor systems. In particular, the invention relates to data type checking using a tagged array architecture.
2. Description of Related Art
Specific implementations of high performance microprocessors tend to exploit the particular design aspects in order to achieve high performance or other design objectives. These implementations usually involve different internal data representations. The incompatibility of the internal data representations between different implementations causes many problems including incorrect and/or unexpected results.
One of the basic internal representations is the data type of the operands in an operation or instruction. Typical operations or instructions involve two source operands and a destination operand. To maintain consistency of the representation, the types of data at four localities have to match. These localities include the operation itself, the two source operands, and the destination operand. In addition to the data type, the size of the operand is also important. For example, a double-precision floating-point operation expects the two source operands and the destination operand to be represented in a 64-bit floating-point number format. A type or size mismatch is an indication of some kind of error, such as incorrect parameters, programming mistake, etc.
Type checking of data can be enforced through a number of methods. One method is to associate a specific set of registers of predetermined type and size for a predetermined set of instructions. For example, floating-point instructions can only access floating-point registers. The disadvantages of this method include the use of large silicon area for implementing the pre-assigned registers. Another method is the use of compilers to check for data types. The compiler method, however, involves a high overhead for testing data values and results in lower performance. In addition, not all compilers are compatible; therefore, a program that works under one operating system may not work under another operating system.
In pipelined and superscalar microprocessors, the problem of type mismatch is even more difficult. In particular, the prefetching of instructions and out-of-order execution render data type tracking difficult. Other problems associated with instruction decoding and execution also create architectural challenges. Some examples of these problems are aliased register sets, instruction retirement, mispredicted branches, and exception processing.
Therefore there is a need in the technology to provide an efficient method to facilitate data type matching.
SUMMARY OF THE INVENTION
The present invention discloses a method and apparatus for matching data types of operands in an instruction. A type code of an operand used by the instruction is determined. An attribute value of a storage element which corresponds to the operand is read from a speculative array. This attribute value is then compared with the type code.
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Bennett Gerald
Fischer Stephen A.
Heit Eric
Hinton Glenn J.
Pentovski Vladimir
An Meng-Ai T.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Whitmore Stacy
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