Excavating
Patent
1995-08-10
1997-12-02
Beausoliel, Jr., Robert W.
Excavating
371 671, 364717, G06F 1110
Patent
active
056944004
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a device and a method for checking data having check bits stored into a transit memory using a checker in accordance with the conception part of the first claim.
Data transmission between two data buses using a buffer memory is appropriate if the two buses are operating asynchronously, i.e. if they are timed by different timing signals. The buffer memory used in this form of data transmission is a FIFO (first-in, first-out) or memory stack device, into which the data are written to the one bus and from which they are read out from the other bus after a short delay. The two different timing signals are prevented from influencing one another through the use of this buffer memory.
It is already known how to determine whether the data in the buffer memory have been read in completely, at the correct place and in the correct sequence. To this end, parity or check bits were, in the past, stored with the data read in. The parity or check bits are used after the data are read to verify the correctness of the data and to correct them, where necessary.
A different solution is known from European Patent Application no. EP-A-0 463 210 (IBM). This discloses a method by means of which the individual bits of the address of the cell's in the memory where the data are stored are logically combined with some of the bits of the data read into the stack in accordance with an exclusive-OR operation. As the data are read out, the logically combined bits are logically combined again with the bits of the cell address in accordance with an exclusive-OR operation and the parity of the data is checked. A mismatch in the parity indicates an error in the memory device.
These methods have the disadvantage that they only check whether the cells in the memory are operating correctly: there is no verification of whether the data were written into the correct memory cells or read out from the correct memory cells. It could clearly be the case that the address logic that generates the addresses of the memory cells has generated incorrect addresses or that the write enable line between the address logic and the memory array is defective. Such errors impair the integrity of the data, in that incorrect data with correct parity of check bit can be read out from the buffer memory without the knowledge of the user or the system.
The objective of the invention therefore is to specify a device and a method to check the functioning of the address logic and of the memory.
This objective is achieved in that a different code is generated for the same address line on the subsequent pass through the memory stack. The use of different codes for each pass has the advantage that the address generation mechanism and the write enable line of the memory stack are subjected to a check. In one embodiment, the code generation method is selected such that memory addresses the interval between which is divisible by 2 are assigned different codes.
In a preferred embodiment, the logical gates are exclusive-OR gates and the first and second code generators are counters.
The object is further achieved by means of a method for checking the data having parity bits and written into a memory stack with one or more address lines comprising the following stages: code generator in accordance with a first logical operation; generated by a second code generator, which code is matched With the code generated by the first code generator in accordance with a second logical operation; being generated for the same address line on a subsequent pass through the memory stack.
In the preferred embodiment, the first and the second code generators generate continuous binary numbers and the individual bits of the binary number are combined with one of the memory in or memory out lines in accordance with the first or second logical operation respectively. The logical operations are preferably exclusive-OR operations. The data are checked for parity.
The invention will be described in further detail below on the basis of the practical example illustrated in the drawi
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Gervais Gilles
Holm Ingemar
Koehler Thomas
Kohler Helmut
Schumacher Norbert
Beausoliel, Jr. Robert W.
Galasso Raymond M.
International Business Machines - Corporation
Iqbal Nadeem
Samodovitz Arthur J.
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