Checkboard memory self-test

Details Checkboard memory self-test Checkboard memory self-test

1989-10-06

1992-03-31

Smith, Jerry

Excavating

371 212, G11C 2900

Patent

active

051014092

ABSTRACT:
The invention is a system and method for high-efficiency checkerboard memory self-test. A random pattern generator configuration includes a linear feedback shift register and a multiple input signature register. The random pattern generator is used to step through the memory addresses in generating the checkerboard pattern. The two least significant address lines connecting the random pattern generator and the memory array are connected together via an exclusive OR gate. Because these address lines indicate the parity of the current and next memory addresses to be generated in the random pattern generator, the output of the exclusive OR gate indicates whether the next memory address to be generated is of the same or different type of state compared to the current memory address. The output of the exclusive OR gate can thus be connected to the data input shift register of the memory array to permit conditional shifting of the checkerboard data pattern into the memory array. One logic state is input to the current memory address when the output of the exclusive OR gate is a logical one and the other logical state is input to the current memory address when the output of the exclusive OR gate is a logical zero.

REFERENCES:
patent: 3758759 (1973-09-01), Boisvert, Jr. et al.
patent: 3761695 (1973-04-01), Eickelberger
patent: 3783254 (1974-01-01), Eichelberger et al.
patent: 4282584 (1981-08-01), Brown et al.
patent: 4300234 (1981-11-01), Marugama et al.
patent: 4502131 (1985-02-01), Giebel
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytsky
patent: 4597080 (1986-06-01), Thatte et al.
patent: 4601034 (1986-07-01), Sridhar
patent: 4654849 (1987-03-01), White et al.
patent: 4701919 (1987-10-01), Naitoh et al.
patent: 4754215 (1988-06-01), Kawai
patent: 4775977 (1988-10-01), Dehara
patent: 4782487 (1988-11-01), Smelser
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 4903266 (1990-02-01), Hack
McCluskey, E. J., "Built-In Self-Test Techniques," IEEE Design and Test, Apr. 1985, pp. 21-28.
Wang L. and E. J. McClusky "Feedback Shift Registor for Self-Testing Circuits", USLI Systems Design, Dec. 1986, pp. 50-58.
E. J. McCluskey and S. Bozongin Neshat, "Design for Autonomous Test," IEEE Transactions on Computers, vol. C-30, No. 11, Nov. 1981, pp. 866-875.
P. H. Bardell & W. H. McAnney, "Pseudorandium Arrays for Built-In Tests", IEEE Transactions on Computers, vol. C-35, No. 7, Jul. 1986, pp. 653-658.
TU9-87-012 "Memory Self-Test", Patent Application, G. E. Hack, No. 187, 708 Dated Filed 4/29/88.
IBM Technical Disclosure Bulletin, C. F. Mejwera, Jr. "Pattern Generator for Memory Test System", (vol. 26, No. 3A, Aug. 1983), p. 1078.
IBM Technical Disclosure Bulletin, vol. 21, No. 12, May, 1979, S. D. Kelly, "Imbedded Memory Test Methods", pp. 4911-4922.

Affiliated with

Also associated with

Rating

Checkboard memory self-test does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Checkboard memory self-test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Checkboard memory self-test will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2264827