Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2000-11-10
2003-02-25
Oda, Christine (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S719000
Reexamination Certificate
active
06525548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a check pattern for a semiconductor device, and more particularly to a check pattern for evaluating the result of via openings during fabrication of semiconductor devices.
2. Terminology
Via Opening
This is herein used to mean a through hole and a contact hole which are formed during fabrication of semiconductor devices.
3. Description of the Related Art
A known manner of evaluating the result of via openings is to measure electrical resistance of a pattern connecting such via openings in series.
FIG. 3
provides one example of a known check pattern for evaluating via openings. The check pattern connects via openings in series. As illustrated in
FIG. 3
, a via opening
101
interconnects an upper layer
111
of conductor lines and a lower layer
121
of conductor line. Within the upper layer
111
, a terminal E is connected to the conductor lines. A via opening
102
interconnects the lower layer
121
and an upper layer
112
of conductor lines. A via opening
103
interconnects the upper layer
112
and a lower layer
122
of conductor lines. A via opening
104
interconnects the lower layer
122
and an upper layer
113
of conductor lines. A via opening
105
interconnects the upper layer
113
and a lower layer
123
of conductor lines. A via opening
106
interconnects the lower layer
123
and an upper layer
114
of conductor lines. Within the upper layer
114
, a terminal F is connected to the conductor lines. In this manner, the pattern interconnects the terminals E and F.
A conventional measuring method using this check pattern may receive an influence due to variation of wiring resistance and/or contact resistance between measuring probes and terminals, and involves difficulty in detecting, with good accuracy, a small variation of resistance via openings.
An object of the present invention is to provide a check pattern for a semiconductor device, with which a small variation of resistance of via opening can be detected without receiving any influence due to variation of wiring resistance and/or contact resistance between measuring probes and terminals.
SUMMARY OF THE INVENTION
According to one exemplary implementation of the invention, there is provided a check pattern for a semiconductor device comprising a plurality groups of via openings, each group interconnecting first and second conductor layer means to define one side of a Wheatstone bridge circuit.
According to the specific aspect of the present invention, the bridge circuit includes a first terminal, a second terminal, a third terminal, and a fourth terminal.
The bridge circuit includes a first group of via openings consisting of a first sub-group and a second sub-group. The first sub-group of the first group interconnects a first upper conductor layer including the first terminal and a first lower conductor layer. The second sub-group of the first group interconnects the first lower conductor layer and a second upper conductor layer including the second terminal. The first upper conductor layer, the first group of via openings, the first lower conductor layer and the second upper conductor layer cooperate with each other to provide first resistance of a first electrical path interconnecting the first and second terminals.
The bridge circuit also includes a second group of via openings consisting of a first sub-group and a second sub-group. The first sub-group of the second group interconnects the second upper conductor layer and a second lower conductor layer. The second sub-group of the second group interconnects the second lower conductor layer and a third upper conductor layer including the third terminal. The second upper conductor layer, the second group of via openings, the second lower conductor layer and the third upper conductor layer cooperate with each other to provide second resistance of a second electrical path interconnecting the second and third terminals.
The bridge circuit includes a third group of via openings consisting of a first sub-group and a second sub-group, The first sub-group of the third group interconnects the first upper conductor layer and a third lower conductor layer. The second sub-group of the third group interconnects the third is lower conductor layer and a fourth upper conductor layer including the fourth terminal. The first upper conductor layer, the third group of via openings, the third lower conductor layer and the fourth upper conductor layer cooperate with each other to provide third resistance of a third electrical path interconnecting said first and fourth terminals.
The bridge circuit includes a fourth group of via openings consisting of a first sub-group and a second sub-group. The first sub-group of the fourth group interconnects the fourth upper conductor layer and a fourth lower conductor layer. The second sub-group of the fourth group interconnects the fourth lower conductor layer and the third upper conductor layer. The fourth upper conductor layer, the fourth group of via openings, the fourth lower conductor layer and the third upper conductor layer cooperate with each other to provide fourth resistance of a fourth electrical path interconnecting the fourth and third terminals.
REFERENCES:
patent: 5640097 (1997-06-01), Hada
patent: 5777486 (1998-07-01), Hsu
patent: 5900735 (1999-05-01), Yamamoto
patent: 6022644 (2000-02-01), Lin et al.
patent: 6127733 (2000-10-01), Kinoshita
patent: 6353235 (2002-03-01), Watanabe
NEC Corporation
Oda Christine
Sundaram T. R.
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