Check bit code circuit for simultaneous single bit error correct

Details Check bit code circuit for simultaneous single bit error correct Check bit code circuit for simultaneous single bit error correct

1993-11-05

1995-10-10

Baker, Stephen M.

Excavating

371 374, 371 376, 371 381, 371 404, H03M 1300, G06F 1110

Patent

active

054577020

ABSTRACT:
A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates partition check bits and burst check bits based on a H-parity matrix data regeneration scheme which provides an a single error correction and multiple bit error detection code which is linear and has the property of self orthogonality within a subclass of self orthogonal codes exclusive of Latin square codes. These check bits provide two independent sources for ascertaining the correct value for any given data bit. An error corrector and detector takes as input the data bits and check bits and provides a corrected data bit output as well as a set of error status lines. The error corrector and detector consists of Error Corrector, error corrector/detector and Error Status modules. The Error Corrector and error corrector/detector modules run in parallel providing a high speed Error Correction and Detection implementation, and providing a simplicity of logic structure compatible with application specific integrated circuit (ASIC) design and production processes.

REFERENCES:
patent: 3582878 (1971-06-01), Bossen
patent: 3601798 (1971-08-01), Hsiao
patent: 3634821 (1972-01-01), Bossen
patent: 4961193 (1990-10-01), Debord et al.
patent: 4993028 (1991-02-01), Hillis
patent: 5251219 (1993-10-01), Babb
Hsiao, M. Y., Bossen, D. C. and Chien, R. T., "Orthogonal Latin Square Co", IBM Journal of Research Development, Jul. 1970, pp. 390-394.

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