Multiplex communications – Wide area network – Packet switching
Patent
1994-01-28
1996-01-16
Ray, Gopal C.
Multiplex communications
Wide area network
Packet switching
39518202, 395858, 395309, 370 16, 364268, 3642687, 3642689, 3642692, 36424294, 364DIG1, G06F 1120, H04L 2914, H04L 1240
Patent
active
054855764
ABSTRACT:
A fault tolerant system management bus architecture for a networking chassis includes a primary path for transmission of system management information and a secondary path for transmission of system management information in the event of failure of the primary path. The primary path includes a first microprocessor controller, coupled between the first system management bus and the processor located on a networking module. The secondary path for transmission of system management information includes a second microprocessor controller system and a dual-port memory. The second microprocessor control system is coupled to the second system management bus and to the dual-port memory. The dual-port memory is also coupled to the processor located on the networking module. The dual-port memory provides the interface between the CPU in the networking module and the second microprocessor control system, thus providing isolation and allowing the memory to be accessible by either processor. Environmental information and module identification information are stored in the dual-port memory. In the event of failure of the primary transmission path, the environmental information and module identification information can be accessed and transmitted over the backup transmission path.
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Fee Brendan
Oliver Chris
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