Charging pump circuit and a phase-locked loop circuit using the

Details Charging pump circuit and a phase-locked loop circuit using the Charging pump circuit and a phase-locked loop circuit using the

1997-07-30

1999-04-27

Je, Dinh

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327536, 327537, 327156, 327148, 327147, 331 17, 331 8, H03L 7089, H03L 708

Patent

active

058983368

ABSTRACT:
An improved charging pump circuit includes first, second, third and fourth switches connected together in series across an associated power supply, a first capacitor connected between the first and second switches and the ground, and a second capacitor connected between the third and fourth switches and the ground. One of the first and second switches responds to a first drive signal for turning into a conductive condition while holding the other switch in a non-conductive condition. Likewise, one of the third and fourth switches responds to a second drive signal for turning into the conductive condition while holding the other switch in a non-conductive condition. The time spent for charging or discharging the load capacitor can be substantially reduced by using the first and second capacitors whose capacitances are much smaller than the capacitance of a load capacitor, and accordingly jitter can be reduced in a PPL circuit in which the charging pump circuit is included.

REFERENCES:
patent: 5136260 (1992-08-01), Yousefi-Elezei
by Deog-Kyoon Jeong et al., "Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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