Charging of a bootstrap capacitance through an LDMOS

Details Charging of a bootstrap capacitance through an LDMOS Charging of a bootstrap capacitance through an LDMOS

1996-05-13

1999-03-16

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With bootstrap circuit

327427, 327537, 327390, A02M 7162

Patent

active

058835474

ABSTRACT:
A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold. Moreover, the body voltage (VB) is prevented from exceeding the source voltage (VS) plus a Vbe, by controlling a discharge path (T2) with a control stage (T1, R1) in response to a drop of the voltage on the limiting resistance (R). This body voltage control circuit is enabled by a second switch (INT2) driven in phase with the first switch (INT1).

REFERENCES:
patent: 4188550 (1980-02-01), Lum
patent: 4346310 (1982-08-01), Carter
patent: 4574203 (1986-03-01), Baba
patent: 5138200 (1992-08-01), Barsanti et al.
patent: 5321313 (1994-06-01), Oberhauser
patent: 5365118 (1994-11-01), Wilcox
patent: 5506539 (1996-04-01), Kelly et al.
patent: 5650737 (1997-07-01), Eilley
patent: 5742196 (1998-04-01), Fronen et al.

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