Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-05-31
2002-10-01
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120, C324S765010
Reexamination Certificate
active
06459282
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a charged particle beam test system for testing an electronics circuit, and more particularly, to a charged particle beam test system for testing a semiconductor integrated circuit by sampling electric potentials on a surface of the integrated circuit with improved accuracy and efficiency.
BACKGROUND OF THE INVENTION
As one of the methods for testing semiconductor devices such as a very large scale integrated circuit (VLSI), a charged particle beam test system may be used to monitor voltages of internal nodes of the VLSI. A charged particle beam, such as an electron beam, is irradiated onto the surface of an integrated circuit under test (DUT) and the resultant secondary electron which represents the voltages and other states of the DUT is detected, thereby obtaining a voltage contrast image of the DUT on a display. A charged particle beam test system is advantageous for testing high density and complex semiconductor chips because it can test such semiconductor chips without physically contacting the chips for probing input/output signals.
In a modern charged particle beam test system, a charged particle beam tester and an IC tester interact with each other to analyze the performance of a DUT. As is well known in the art, an IC tester provides a test pattern signal (also called a test vector) to a DUT and compares the resultant output signal from the DUT with an expected value signal. Such a comparison is made at a timing predetermined by a comparison enable signal provided in a test program. If the output signal from the DUT is different from the expected value signal, the IC tester generates a fail signal.
In a charged particle beam test system having an IC tester, a DUT is placed on an X-Y stage of the charged particle beam column. The DUT is provided with a test pattern signal from the IC tester and the resultant output signal of the DUT is compared with the expected value signal as noted above by the IC tester. At the same time, the specified portion of the DUT which is being tested by the IC tester is also tested by the charged particle beam tester by being irradiated with the charged particle beam and the resultant secondary electron is detected. In this manner, in a charged particle beam test system, test result data is acquired concerning the DUT's output signal produced in response to the test pattern signal as well as concerning the potential contrast of the inner nodes of the DUT relative to the test pattern, resulting in a highly sophisticated and efficient evaluation of the DUT performance.
An example of such a charged particle beam test system in the conventional technology is shown in FIG.
5
.
FIG. 6
is a timing chart showing the timing relationship between trigger signals, sampling pulses (charged particle beam pulses) and pass/fail signals in the charged particle beam test system of FIG.
5
.
FIGS. 4A and 4B
are schematic diagram showing sampled waveforms relative to the timings of the sampling pulses.
In the example of
FIG. 5
, the charged particle beam test system is formed with a charged particle beam tester EBT such as an electron beam tester and an IC tester
40
. The charged particle beam tester EBT includes a sampling pulse generator
50
, a charged particle beam column
60
, a signal processor
70
, a test result memory
80
, and a controller
90
. The charged particle beam column
60
includes a charged particle beam generator such as an electron gun
62
, a beam blanker
64
, and a secondary electron detector
68
. At the bottom of the column
60
, an X-Y stage
67
is provided to place a semiconductor device under test (DUT) thereon.
A charged particle beam such as an electron beam emitted from the electron gun
62
irradiates the surface of the DUT through the beam blanker
64
. The beam blanker
64
controls blanking of the charged particle beam from the electron gun
62
thereby producing a pulsed charged particle beam
61
. By moving the X-Y stage
67
in the X and Y directions, the irradiating position of the charged particle beam on the surface of the DUT can be controlled. The signal processor
70
provides a control signal which is provided to the grid
66
to control the amount of secondary electron emitted from the DUT. The secondary electron is detected and integrated by the secondary electron detector
68
.
The IC tester
40
provides a test pattern signal
48
with predetermined timings to one or more terminals of the DUT and evaluates the resultant signals from the DUT by comparing the same with the expected value signals. The IC tester
40
also provides a trigger signal
41
to the sampling pulse generator
50
to synchronize the test pattern signal
48
to the DUT with the pulsed charged particle beam
61
irradiated on the DUT. To define the timings of such comparison operations between the DUT's output signal and the expected value signal, the test program used in the IC tester includes several comparator enable (CPE) signals for each time interval between the two trigger signals
41
.
The IC tester
40
also sends a fail signal
42
and a clock signal
49
to the charged particle beam tester EBT. The clock signal
49
, in this case, is a tester rate clock which defines a test cycle of the IC tester
40
. Although not shown in the drawings, a plurality of test cycles are included within each cycle of the trigger signals
41
.
In the arrangement of
FIG. 5
, the IC tester
40
sends the trigger signal
41
to the charged particle beam tester EBT at a predetermined timing relationship with the test pattern signal
48
as shown in FIG.
6
A. As noted above, the test program is designed to generate one or more comparator enable signals (CPE) within the trigger cycle as shown in FIG.
6
C. Thus, at the timing of the CPE, i.e., for the test cycle having the CPE, the DUT output signal is compared with the expected data signal and a fail signal
42
is generated in the case where the DUT output signal does not match the expected data signal. In the actual test system, the fail signal
42
is produced several cycles later than the test cycle in which the DUT output fails.
The sampling pulse generator
50
includes a delay circuit and generates a sampling pulse
51
at a specified delay time Td after the trigger signal
41
from the IC tester
40
. The sampling pulse
51
drives the charged particle beam blanker
64
, thus, the column
60
generates the charged particle beam pulse
61
as shown in FIG.
6
B. Consequently, the charged particle beam (such as electron beam) pulse
61
is generated at the timing of the sampling pulse
51
, which is irradiated on the specified position of the DUT.
In an actual test system, to improve the measurement accuracy, the sampling pulse
51
(beam pulse
61
) is repeatedly irradiated on the DUT at the fixed timing Td from the trigger signal
41
. For example, the same sampling pulse
51
is repeated by several ten to several thousand times and the data detected by the secondary electron detector
68
is integrated during this period. Namely, the secondary electron detector
68
, which is for example, a scintillator or a photomultiplier, converts the detected secondary electron to an electric signal representing the amount of secondary electron and integrates the detected signals for the number of beam pulses supplied to the DUT.
The controller
90
controls the overall process of the charged particle beam tester EBT. For example, the controller
90
sets the delay time Td in the sampling pulse generator
50
. After acquiring the number of data for the sampling pulses
51
which is delayed by Td from the trigger signal
41
, the controller
90
slightly changes the delay time Td relative to the trigger signal
41
as shown in
FIG. 4A
to collect the data by repeatedly applying the beam pulse
61
at this timing. By repeating this process while slightly changing the delay time Td, the waveform data such as shown in
FIGS. 4A and 4B
are acquired and stored in the test result memory
80
.
The signal processor receives the trigger signal
41
Advantest Corp.
Muramatsu & Associates
Nguyen Vinh P.
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