Radiant energy – Irradiation of objects or material – Irradiation of semiconductor devices
Reexamination Certificate
2000-10-13
2001-07-03
Berman, Jack (Department: 2881)
Radiant energy
Irradiation of objects or material
Irradiation of semiconductor devices
C355S053000, C430S030000
Reexamination Certificate
active
06255663
ABSTRACT:
INCORPORATION BY REFERENCE
This application is based on Japanese Patent Application No. 11-35526, filed Feb. 15, 1999 and Japanese Patent Application No.11-100894, filed Apr. 8, 1999 and its contents are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charged particle beam exposure apparatus for exposing a sensitive substrate such as a wafer etc. with an image of a pattern formed on a mask or reticle using a charged particle beam.
2. Related Art
Conventional exposure methods for charged particle beam exposure apparatus can be classified into the following three types.
(1) Spot beam exposure methods
(2) Variable-shaped beam exposure methods
(3) Block exposure methods
These methods of exposure provide excellent resolution when compared to conventional batch transfer methods employing light, but this was provided at the expense of throughput. In particular, with the exposure methods of (1) and (2), throughput is limited because exposure is carried out so as to trace a pattern with a spot of an extremely small spot diameter or with a rectangular beam. Further, the block exposure method of (3) has been developed in order to improve the throughput. Here, a standardized pattern is made into a mask and throughput is improved by batch-projecting this pattern. However, since in this method the number of patterns that can be made into masks is limited, it is necessary to use the variable-shaped beam exposure method together with the block exposure method of (3). Throughput is therefore not improved to the anticipated extent.
In order to improve the poor throughput of conventional charged particle beam exposure apparatus, divided projection exposure apparatus in which a substrate is projected and exposed with an image of a pattern formed in a portion of reticle are being developed.
With this divided projection exposure apparatus, a plurality of chips are formed on a sensitive substrate (usually a wafer). Regions of each chip are partitioned into a plurality of stripes, and each stripe is divided into a plurality of sub-fields. On the other hand, patterns to be transferred to the chips of the sensitive substrate are formed at the reticles and these patterns are similarly divided into stripes and sub-fields corresponding to the stripes and sub-fields of the chips.
An exposure method employing an electron beam will be explained. A reticle stage mounted with a reticle and a wafer stage mounted with a wafer are moved at a fixed speed in accordance with the rate of reduction for pattern projection. At this time, an optical axis of the exposure apparatus passes through each center of stripes of the reticle and the chip. A sub-field on the reticle is irradiated with the electron beam and a pattern formed on the reticle is projected onto the sensitive substrate by an optical projection system so that the sensitive substrate is exposed with an image of the pattern.
The electron beam is then deflected in a direction substantially at right angles to the direction of progression of the reticle stage, and the pattern of the mask sub-fields arranged in a line are sequentially projected upon the sensitive substrate so that the sensitive substrate is exposed with the pattern image. When projection exposure of the line of mask sub-fields is complete, projection exposure of the next line of mask sub-fields begins. The direction of deflection of the electron beam is reversed for each line and the patterns of mask sub-fields are sequentially projected in order that throughput is increases.
By carrying out exposure using this method, compared to conventional charged particle beam exposure apparatus, each of mask sub-field regions is collectively irradiated with the electron beam so that the sensitive substrate is exposed with an image of the pattern in each mask sub-field. And all patterns with which a sensitive substrate is exposed are formed on the reticle so that throughput can be increased substantially as a result.
Optical projection systems for exposure apparatus employing electron beams consist of lenses and deflectors, etc. However, magnetic fields other than the deflecting field by the deflectors are also generated at the same time due to the setting of the semi-angles of the deflecting coils and the setting of the current flowing in each deflecting coil. If magnetic field distribution is expressed with a cylindrical coordinate system (z, r, &thgr;) taking the angle of rotation about the optical axis as &thgr;, the deflection field can be expressed in a form combining components proportional to the lowest order trigonometric functions cos [&thgr;], sin [&thgr;]. However, the magnetic field for other than the deflection field is expressed by combining components proportional to odd-numbered order trigonometric functions of cos [3&thgr;], sin [3&thgr;] and cos [5&thgr;], and sin [5&thgr;], etc.
These high-order components do not contribute to electron beam deflection but do cause a group of aberrations referred to as a so-called “four-fold aberrations”. These four-fold aberrations cause the image of the electron beam to blur and cause the shape of the projected image to become distorted. This causes undesirable disconnection in an integrated circuit formed on the wafer surface or changes in shape. These four-fold aberrations also occur for deflectors designed so that the 3&thgr; component and 5&thgr; component of the magnetic field become substantially zero. Conventionally, it has been considered that errors in assembly of the deflectors causes magnetic fields of the 3&thgr; component and the 5&thgr; component. Therefore, attempts have been made to improve the precision with which the coils are made and the deflectors are assembled. However, such efforts have not brought sufficient results.
This kind of problem does not just occur for exposure apparatus employing electron beams, but also occurs when other charged particle beams are employed.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to provide a charged particle beam exposure apparatus where the four-fold aberrations generated by the deflectors are reduced.
It is a further object of the present invention to provide a highly integrated semiconductor device with a very small line width and a semiconductor device manufacturing method capable of manufacturing this kind of semiconductor device.
In order to achieve the aforementioned objects, with a charged particle beam exposure apparatus according to the present invention, semi-angles and ratio of ampere-turn values of deflecting coils of at least one of the deflectors are set in such a manner that a 3&thgr; component, 5&thgr; component and 7&thgr; component of a magnetic field generated by the deflectors become substantially zero. The four-fold aberrations caused by the 3&thgr; component, 5&thgr; component and 7&thgr; component of the magnetic field can therefore be made substantially zero.
The deflector comprises n(n≧2) sets of deflecting coils with a semi-angle &thgr;i of substantially 180°×i/(2n+1) (i=1~n). The ratio of ampere-turn value Ji of each deflecting coil i is then set in such a manner that the following equations (1) and (2) are substantially fulfilled with respect to each integer k from 1 to m. Here, the value of m is set to an arbitrary integer between a minimum value 3 (except that 1 when n=2 and 2 when n=3) and a maximum value (n−1).
The deflector may comprise n(n≧3) sets of deflecting coils with a semi-angle &thgr;i of substantially 180°×(i−½)/(2n−1) (i=1~n). The ratio of ampere-turn value Ji of each deflecting coil i is then set in such a manner that the following equations (1) and (2) are substantially fulfilled with respect to each integer k from 1 to m. Here, the value of m is set to an arbitrary integer between a minimum value 3 (except that 2 when n=3) and a maximum value (n−1).
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Kamijo Koichi
Yamada Atsushi
Berman Jack
Nikon Corporation
Oliff & Berridg,e PLC
Smith II Johnnie L
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