Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
1999-06-25
2002-01-01
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S296000, C430S942000
Reexamination Certificate
active
06335127
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a charged beam exposure technique in lithography of the manufacture of electronic devices such as semiconductor devices and, more particularly, to a mask used in exposing a wafer with a charged beam, a charged beam exposure apparatus using this mask, and a device manufacturing method employing this apparatus.
In mass production of semiconductor memory devices, an optical stepper having high productivity has been used. In production of next-generation memory devices of 1-gigabit or 4-gigabit DRAMs having a line width of 0.2 &mgr;m or less, the high-productivity electron beam exposure method having high resolving power is expected as one of the exposure techniques that replace the optical exposure system.
The conventional electron beam exposure method is mainly performed using a Gaussian beam or variable shaped beam system, and accordingly has a low productivity. Therefore, the electron beam exposure method has been used in applications such as mask drawing, research and development of VLSIs, and exposure of ASIC devices on small-lot production, by effectively using the characteristics of the excellent resolving performance of the electron beam.
To apply the electron beam exposure method to mass production in this manner, how to increase its productivity is a significant problem. In a conventional electron beam exposure apparatus, the exposure region of an electron optical system that can be exposed by one shot is extremely smaller than the exposure region of the projection optical system of an optical exposure apparatus. To expose the wafer entirely takes a very long period of time since the distances of electronic scanning and mechanical scanning become longer than in the optical exposure apparatus, resulting in an extremely low throughput. To increase the throughput, either the electronic scanning speed and the mechanical scanning speed must be further increased greatly, or the one-shot exposure region must be enlarged greatly.
As one of methods that solve this problem of throughput increase while maintaining a necessary resolving power, a following method is discussed. According to this method, a circuit pattern to be exposed onto a silicon wafer is formed on a mask. An electron beam having an enlarged exposure region irradiates the mask, so that the mask pattern is projected onto the wafer. As the electron beam having an enlarged exposure region, one having a rectangular spot is usually used. In the electron beam exposure apparatus shown in
FIG. 18
, the beam has an arcuate spot to decrease the curvature of field, so that the exposure region is further increased, thereby solving the above problem.
FIG. 18
shows an electron gun
101
, an electron beam
602
, an axis
120
of an electron optical system, a condenser lens
103
, an aperture
104
, a mask
605
, an aberration correcting optical system
107
, electron lenses
108
A and
108
B, a scattered electron limiting aperture
111
, a wafer
114
, a moving direction
121
of the mask stage at a certain time point, a moving direction
122
of the wafer stage at a certain time point, an aperture opening
201
, an electron beam irradiated region
202
on the mask, a device pattern
603
on the wafer, and a region
604
to be irradiated with an electron beam by wafer moving.
The electron beam mask used in this electron beam exposure apparatus has a circuit pattern the size of which depends on the magnification of the projection system of the electron beam exposure apparatus and is usually twice to 5 times that of the circuit pattern on the silicon wafer. For example, it is said that a circuit pattern corresponding to one 4-gigabit DRAM chip requires an area of about 20 mm×35 mm. The area of the circuit pattern on the mask used for exposing this circuit pattern is 80 mm×140 mm when the magnification of the projection system is ¼. It is difficult to form a circuit pattern of this size on one thin film portion
605
a
surrounded by a reinforced portion
606
a
on the mask, as shown in
FIG. 19A
, with a sufficiently large strength and sufficiently high precision. Hence, as schematically shown in
FIG. 19B
, this circuit pattern is divisionally formed on a plurality of thin film portions
605
b
into a plurality of chip patterns M
1
to M
9
, and the respective divided chip patterns are reinforced with a rectangular bar portion
606
b
(the portion will be referred to as a strut hereinafter).
To expose the chip patterns M
1
to M
9
divided on the mask onto the wafer, as shown in
FIG. 20A
, the mask stage is moved with respect to an electron beam
602
a
having a fixed irradiation position. The group of divided chip patterns on the mask, which is to be irradiated with the electron beam
602
a
by one moving operation of the mask stage in an X direction shown in
FIG. 20A
, is called “divided chip patterns on a stripe”. For example, the divided chip patterns M
1
, M
2
, and M
3
exist on the same stripe. The mask stage moves in the direction of an arrow A such that the electron beam
602
a
moves across the respective stripes. In synchronism with this, the wafer stage is moved in the direction of an arrow B (FIG.
20
B). When the electron beam is deflected by a deflector not shown in
FIG. 18
, the patterns are stitched to each other such that the bars among the divided patterns on the same stripe on the mask do not appear on the reduced pattern on the wafer
114
. When the mask stage and wafer stage are moved up to the first pattern on each stripe, the patterns among the stripes are stitched to each other such that bars among the stripes on the mask do not appear on the reduced pattern on the wafer
114
. The divided chip patterns M
1
, M
2
, . . . on the mask in
FIG. 20A
are reduced on the wafer
114
of FIG.
20
B and are stitched to each other as patterns W
1
, W
2
, . . . . When the above operation is repeated, a plurality of device chip patterns
603
, each consisting of the plurality of divided chip patterns and corresponding to one chip, are exposed onto the wafer
114
.
The following problem, however, arises. That is, if the electron beam width is larger than the width of struts among the divided patterns on one stripe on the mask, the total dose varies, and the position of the transfer pattern is partially shifted. This problem will be described using a rectangular beam spot with reference to FIG.
21
.
Referring to
FIG. 21
, reference numeral Bw
1
denotes the width of a rectangular cross-sectional electron beam
602
c
on the mask
605
; s
1
, the width of a strut between divided patterns within one stripe on the mask; and sw
1
, the length of a portion on the wafer which corresponds to a strut width s
1
of the mask. Reference numerals M
1
to M
9
denote respective divided patterns on the mask; and W
1
to W
3
, transfer patterns on the wafer that correspond to the divided patterns M
1
to M
3
of the mask.
Referring to
FIG. 21
, chart I schematically shows the distribution of an exposure dose on the wafer obtained when transferring the divided pattern M
1
on the mask
605
. In chart I, the axis of abscissa represents the positions of the transfer patterns W
1
, W
2
, and W
3
on the wafer that correspond to the divided patterns M
1
, M
2
and M
3
on the mask during exposure, and the axis of ordinate represents the dose at each position. If the beam width on the mask is larger than the strut width, i.e., if Bw
1
>s
1
, the divided pattern M
2
is partly exposed undesirably immediately before exposure of the pattern M
1
is ended. Accordingly, as shown in chart I, the divided pattern M
2
which should not be originally transferred is partly transferred to a position shifted from the transfer pattern W
1
by sw
1
within the transfer pattern W
2
on the wafer. Similarly, when exposing the divided pattern M
2
, as shown in chart II, the divided pattern M
3
is partly transferred to a position shifted from the transfer pattern W
2
by sw
1
within the transfer pattern W
3
on the wafer. Chart IV shows the tot
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