Radiant energy – Irradiation of objects or material – Irradiation of semiconductor devices
Reexamination Certificate
1999-07-30
2001-08-07
Nguyen, Kiet T. (Department: 2881)
Radiant energy
Irradiation of objects or material
Irradiation of semiconductor devices
C250S398000
Reexamination Certificate
active
06271531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charged beam drawing apparatus and method thereof.
2. Description of the Related Art
In recent years, as semiconductor devices are complicatedly structured, a charged particle beam (for example, an electron beam) has been used to expose a resist which is applied on a wafer.
When a wafer is divided into a plurality of pieces in a chip size, the surface of the wafer includes a chip area in which to-be-manufactured chips (device chip) are formed and a peripheral area in which peripheral chips (not to be manufactured owing to their incompleteness of the form) are formed.
An area of a single peripheral chip is smaller than that of a device chip. Therefore, if an electron beam is irradiated onto the peripheral area based on the same exposure data as the chip area, the electron beam may possibly be irradiated onto a wafer holder for holding the wafer.
If the electron beam is irradiated onto the wafer holder, oil mist composed of a very small amount of organic matter is printed on a wafer holder, then an insulating film is formed on the wafer holder. Such insulating film is charged up when irradiating the electron beam onto the following wafer, particularly when exposing the peripheral area. Charging up the insulating film brings about drift of the electron beam. Once the irradiation position of the electron beams is drifted, an irradiation position of the electron beam deviates from its appropriate position. Then, the exposure area of the resist also deviates from an appropriate position, resulting in the resist being patterned inaccurately.
Disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052 is a technique for overcoming the above-described problems. According to the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052, peripheral chips are divided into a plurality of smallest areas onto which the electron beam can still be irradiated, when exposing a peripheral area. The electron beam is controlled not to be irradiated onto the wafer holder and to expose only the peripheral chips. In the exposure of the peripheral area, a positive type resist is applied on the wafer, and the electron beams is irradiated onto the entire peripheral area, so as to remove the resists from the peripheral area.
However, in the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052, there is found such a problem as shown below.
Since the peripheral chips formed in the peripheral area can not be manufactured, a degree of accuracy of the irradiation position and exposure amount when exposing the peripheral area may be lower than a degree thereof when exposing the chip area.
However, according to the above-described technique, the peripheral chips are only divided into a plurality of small areas in order to irradiate the electron beam onto the peripheral chips rather than the onto the wafer holder. Thus, a problematic matter arises in that the electric power is wastefully consumed, and that the throughput of to-be-manufactured semiconductor devices is low.
If the resist on the peripheral area is removed as described above, the side wall of the resist formed in the chip area is exposed. Thus, the side wall of the resist formed in the chip area may be etched, in the etching performed after the resist is removed from the peripheral area.
If the side wall of the resist formed in the chip area is unnecessarily etched as described above, low yield of to-be-manufactured semiconductor devices may problematically be realized.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a charged beam drawing apparatus which is operable at low consumption power.
Another object of the present invention is to provide a charged beam drawing method capable of realizing high throughput of to-be-manufactured semiconductor devices.
Further object thereof is to provide a charged beam drawing method capable of realizing high yield of to-be-manufactured semiconductor devices.
In order to achieve the above-described objects, according to the first aspect of the present invention, there is provided a charged beam drawing apparatus comprising:
a particle source which outputs a charged beam to be irradiated onto a wafer having a surface on which a to-be-exposed resist is applied;
predetermined number of masks each of which has an aperture through which the charged beam can pass;
at least one lens which changes a forward direction of the charged beam and changes a degree of convergence of the charged beam; and
a controller which irradiates the charged beam onto the wafer with predetermined accuracy of an irradiation position of the charged beam and at a predetermined exposure amount, by controlling at least either one of the particle source, the masks, or of the lens, and
wherein the controller irradiates the charged beam onto a peripheral area of the wafer while setting the accuracy of the irradiation position of the charged beam lower, when exposing the peripheral area which is positioned at the periphery of a chip area including to-be-manufactured device chips and in which incomplete peripheral chips not to be manufactured are formed, than the accuracy of the irradiation position thereof when exposing the chip area of the wafer.
According to the present invention, an exposure time for exposing the resist applied on the wafer can be shorter than an exposure time for exposing the resist according to the conventional techniques. For example, in a case where stabilizing operations of the lens (an electromagnetic lens) is quite time consuming, it is required to wait until the lens becomes stable at every shot, for exposing the chip area with high accuracy. It is not required to expose the peripheral area with the same accuracy as the chip area, thus the shorter exposure time can be realized by setting the accuracy of the irradiation position of the charged beam lower.
The controller may irradiate the charged beam onto the peripheral area at the exposure amount which is smaller than the exposure amount when exposing the chip area.
The controller may
control a size of the charged beam by controlling at least either of the mask or of the lens, and
set the exposure amount smaller when exposing the peripheral area, than the exposure amount when exposing the chip area, by expanding the size of the charged beam.
The controller may irradiate the charged beam onto the wafer after a wait time for stabilizing a state of the lens has lapsed, for retaining predetermined accuracy of the irradiation position of the charged beam.
A wait time for stabilizing the state of the lens when exposing the peripheral area may be shorter than a wait time for stabilizing the state of the lens when exposing the chip area.
The controller may scan the peripheral area while irradiating the charged beam onto the peripheral area by controlling the lens.
By doing this, the wait time for the state of the lens to be stable when exposing the peripheral area can substantially be zero, after the irradiation of the charged beam begins.
The particle source may output an electron beam as the charged beam.
According to the second aspect of the present invention, there is provided a charged beam drawing method comprising:
arranging, in a predetermined position, a wafer having a surface on which a to-be-exposed resist is applied; and
exposing the resist with predetermined accuracy of an irradiation position and at a predetermined exposure amount by irradiating the charged beam onto the wafer,
wherein the exposing includes irradiating the charged beam onto a peripheral area of the wafer while setting accuracy of an irradiation position of the charged beam lower when exposing the peripheral area which is positioned at the periphery of a chip area including to-be-manufactured device chips and in which incomplete peripheral chips not to be manufactured are formed, than accuracy of an irradiation position of the charged beam when exposing the chip area of the wafe
McGinn & Gibb PLLC
NEC Corporation
Nguyen Kiet T.
LandOfFree
Charged beam drawing apparatus and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charged beam drawing apparatus and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charged beam drawing apparatus and method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2525655