Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2006-09-12
2006-09-12
Mai, Son (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185270, C365S185280, C365S185290
Reexamination Certificate
active
07106625
ABSTRACT:
A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.
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Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Macronix International Co, td
Mai Son
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