Charge trap-type 3-level non-volatile semiconductor memory...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185030, C365S185180

Reexamination Certificate

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11341341

ABSTRACT:
Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.

REFERENCES:
patent: 5966326 (1999-10-01), Park et al.
patent: 6490204 (2002-12-01), Bloom et al.
patent: 6649972 (2003-11-01), Eitan
patent: 6853587 (2005-02-01), Forbes
patent: 7130215 (2006-10-01), Yeh
patent: 7218554 (2007-05-01), Hsu et al.
patent: 2007/0195597 (2007-08-01), Park et al.
patent: 2005-0040667 (2005-05-01), None
English language abstract of Korean Publication No. 2005-0040667.

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