Charge transferring device and charge transferring method...

Details Charge transferring device and charge transferring method... Charge transferring device and charge transferring method...

1998-10-26

2001-10-30

Munson, Gene M. (Department: 2811)

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Particular input or output means

C257S239000, C257S224000

Reexamination Certificate

active

06310933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge transferring device and a charge transferring method. More particularly, the present invention relates to a charge transferring device and a charge transferring method which have a floating diffusion layer that can reduce a floating diffusion capacitance.
2. Description of the Related Art
Conventionally, a charge transferring device has been well known which has a floating diffusion amplifier composed of a reset MOSFET with a floating diffusion layer and a detection MOSFET that has a gate electrode connected to this floating diffusion layer and constitutes a detection circuit. For example, refer to (“Two Phase Charge Coupled Devices with Overlapping Polysillicon and Aluminum Gates”, Kosonocky, W. F. and Carnes, J. E., RCA Review Vol. 34, pp. 164-201, 1973) and the like.
The charge transferring device having this floating diffusion amplifier will be described below with reference to
FIGS. 1A
,
1
B,
2
and
3
.
FIG. 1A
is a plan view of a floating diffusion layer containing a transferring section of the charge transferring device and the reset MOSFET.
FIG. 1B
is a view diagrammatically showing a section taken on the line I-I′ of FIG.
1
A.
FIG. 2
is a view diagrammatically showing a section taken on the line II-II′ of FIG.
1
A. And,
FIG. 3
is a view diagrammatically showing a section taken on the line III-III′ of FIG.
1
B.
In
FIGS. 1A
,
1
B,
2
and
3
, a reference number
1
denotes a P-type semiconductor substrate. Similarly, a reference number
2
denotes a high concentration P
+
-type semiconductor element separating region having the same conductive type as the P-type semiconductor
1
. A reference number
300
denotes a floating diffusion layer. A reference number
4
denotes an N
+
-type semiconductor region connected to a reset power supply Vrd. A reference number
5
denotes a gate electrode of a detection MOSFET of a detection circuit K connected to the floating diffusion layer
300
. A reference number
6
denotes a gate electrode of a depletion type load MOSFET of the detection circuit K. A reference number
7
denotes an N-type semiconductor region of a known two-phase driving type charge transferring device. A reference number
8
denotes an N
−
-type semiconductor region having the same conductive type as the N-type semiconductor region
7
to protect a signal charge from being transferred to the reverse direction of the two-phase driving type charge transferring device. A reference number
9
denotes a reset gate electrode to which a reset pulse voltage &phgr;R is applied. A reference number
10
denotes a gate electrode to which a low voltage is applied as an output end of the charge transferring device. A reference number
11
is a charge transfer electrode formed of two-layer polycrystal silicon film to which a charge transfer pulse voltage &phgr;
1
is applied. A reference number
12
is a charge transfer electrode formed of two-layer polycrystal silicon film to which a charge transfer pulse voltage &phgr;
2
is applied. A reference number
13
denotes a drain power supply Vd of the detection circuit K. And, a reference number
14
denotes a signal output terminal Vout.
Operations of the charge transferring device having the floating diffusion amplifier will be described below. Immediately before a signal charge is transferred from the charge transferring device to the floating diffusion layer
300
, a high level of the reset pulse voltage &phgr;R is always applied to the reset gate electrode
9
. Accordingly, the floating diffusion layer
300
is reset to the reset voltage Vrd. After the reset pulse voltage &phgr;R is returned back to a low level, the voltage level of the charge transfer electrode
12
changes from a high level to a low level. Then, the signal charge is transferred to the floating diffusion layer
300
.
If a whole capacitance containing the gate electrode
5
of the detection MOSFET connected to the floating diffusion layer
300
is Cfd and the signal charges transferred to the floating diffusion layer
300
is Qsig, a potential change &Dgr;Vfd=Qsig/Cfd is generated in the floating diffusion layer
300
. Then, the potential change &Dgr;Vfd changes the voltage of the gate electrode
5
of the detection MOSFET in the detection circuit K. The potential change &Dgr;Vfd proportional to the transferred signal charges Qsig is detected in the signal output terminal Vout
14
of the detection circuit K.
In order to increase a detection sensitivity, it is necessary to reduce the floating diffusion capacitance Cfd. Japanese Laid Open Patent Application,(JP-A-Heisei 4-23334) discloses that the impurity concentration of the floating diffusion layer
300
decreases with the decrease of the junction capacitance between the floating diffusion layer
300
, and one of the P-type semiconductor substrate
1
, the P
+
-type semiconductor region (the element separating region)
2
surrounding the floating diffusion layer
300
, the reset gate electrode
9
, and the gate electrode
10
.
However, in this case if the impurity concentration of the floating diffusion layer
300
is extremely low , the floating diffusion layer
300
is depleted in a voltage lower than the reset power supply voltage Vrd. Thus, the floating diffusion layer
300
is reset to the voltage lower than the reset power supply voltage Vrd. That is, a reset fault is generated. Therefore, it is necessary to adjust the impurity concentration of the floating diffusion layer
300
.
For this reason, Japanese Examined Open Patent Application,(JP-B-Heisei 8-21709) discloses that the floating diffusion layer
300
is provided with a first N-type semiconductor region
300
a
and a second N-type semiconductor region
300
b
having a concentration higher than that of the first N-type semiconductor region
300
a
as described below. That is, the impurity concentration of the first N-type semiconductor region
300
a
is set to a low impurity concentration at which the first N-type semiconductor region
300
a
is not substantially depleted when the voltage &phgr;R is applied to the reset gate electrode
9
(for example, an impurity concentration of about 1×10
17
atoms/cm
3
) The second N-type semiconductor region
300
b
is provided to be connected to the gate electrode
5
of the detection circuit K by using a metallic wire. The impurity concentration of the second N-type semiconductor region
300
b
is set to be higher than that of the first N-type semiconductor region
300
a
(for example, an impurity concentration of about 1×10
19
atoms /cm
3
)
In
FIGS. 1A
,
1
B,
2
and
3
, the impurity concentration of the first N-type semiconductor region
300
a
is suppressed in a range in which the floating diffusion layer
300
is not depleted in the voltage lower than the reset power supply voltage Vrd. Thus, it is possible to suppress the junction capacitance between the floating diffusion layer
300
and the P-type semiconductor substrate
1
, the junction capacitance between the floating diffusion layer
300
, and one of the element separating region (the P
+
-type semiconductor region)
2
and the reset gate electrode
9
, and the gate electrode
10
. Therefore, the whole floating diffusion capacitance Cfd of the floating diffusion layer
300
is reduced.
The second N-type semiconductor region
300
b
whose impurity concentration is higher than that of the first N-type semiconductor region
300
a
is formed in
FIGS. 1A
,
1
B,
2
and
3
. For the reason, even if an alloy heat treatment of aluminum as the metallic wire is sufficiently performed in a connection section
5
a
to the metallic wire, P-N junction leak is never generated in a portion below the connection section
5
a
. Moreover, the high concentration layer is limited to a narrow region of only the second N-type semiconductor region
300
b
. Therefore, there is no possibility of the large increase in the junction capacitance (the floating diffusion capacitance) Cfd of the f

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