Charge transfer readout circuits

Details Charge transfer readout circuits Charge transfer readout circuits

1976-08-26

1977-10-25

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307221D, 307279, 340173LS, 358213, G11C 706, H04N 314

Patent

active

040558363

ABSTRACT:
During readout, the signals induced on the columns of a charge transfer array cause currents to flow through respective conduction paths of field effect transistors connected to the columns. The threshold voltage V.sub.th of each transistor is compensated for prior to readout by establishing the gate electrode thereof at a quiescent gate bias level V.sub.c +V.sub.th, where V.sub.c is the quiescent voltage at the source electrode of that transistor. The effects of dark current or other fixed signal level it is desired to discriminate against associated with the respective columns of the array, also may be compensated for by reducing the quiescent bias level on the gate electrode by an amount proportional thereto.

REFERENCES:
patent: 3849673 (1974-11-01), Koo
patent: 4011441 (1977-03-01), Michon et al.

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