Charge transfer multiplying feedback A/D converter

Details Charge transfer multiplying feedback A/D converter Charge transfer multiplying feedback A/D converter

1978-06-26

1979-08-14

Miller, Charles D.

Communications: electrical

Audible indication

Percussion-type sound producer

324 57R, H03K 1302

Patent

active

041647343

ABSTRACT:
A charge transfer multiplying feedback A/D converter is provided wherein a CCD component is part of the converter and feeding a source follower and a comparator to provide a charge feedback path into the CCD converter and also to provide a resetting signal to a primary charge storage well within the CCD component. The primary charge storage well has a charge capacity corresponding to one-half of the full scale value of the converter. A charge applied to the converter is indicative of the instantaneous value of an analog input signal to the primary charge storage well. A secondary charge storage well is also provided for temporarily storing excess charges which overflow from the primary charge storage area into such secondary storage well. The converter has built into it a mechanism for sensing the amount of charge stored in the secondary charge storage well and for periodically creating an amount of charge, that is proportional to twice the sensed charge, for transferring same to the primary charge storage well. This converter also has a mechanism for changing a potential barrier level so as to enable the draining of the charge stored in the secondary charge storage well. The CCD component determines whether or not the charge applied to the primary charge storage well exceeds its charge storage capacity. The converter has the ability of draining the charge from the primary charge storage well when overflow charges are sensed and for transferring the charge stored in such primary charge storage well to the secondary charge storage well when overflow charges are not sensed. The converter also includes multiplication capability of charge by way of a feedback loop between an output terminal of the sensed digital signal back to an input gate into the primary charge storage well.

REFERENCES:
patent: 3745555 (1973-07-01), Carbrey
patent: 3842413 (1974-10-01), Lagarde
patent: 3930255 (1975-12-01), Means
patent: 4065766 (1977-12-01), Butler
patent: 4072938 (1978-02-01), Buchanan
patent: 4087812 (1978-05-01), Terman
patent: 4115766 (1978-09-01), Smith
Mok, "Solid-State Electronics", 1974, vol. 17, pp. 1147-1154.

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