Charge transfer memory in serial-parallel-serial organization

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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357 24, 365183, G11C 1928, H01L 2978, G11C 1134

Patent

active

043821936

ABSTRACT:
A serial-parallel-serial organized charge transfer memory is integrated on a semiconductor chip and includes a read-in chain consisting of first and second charge transfer elements alternately arranged behind one another, respectively controllable by way of clock pulse lines, and comprising memory and shift electrodes, and a field of parallel chains of charge transfer elements into which charges characterizing information are transferred either only from the first or only from the second charge transfer elements of the read-in chain, and a read-out chain constructed as the read-in chain and operated by way of clock pulse lines. The like electrodes of the charge transfer elements of the read-in and read-out chains, together with the appertaining control and clock pulse lines respectively consist of a continuous conduction band, at least in the area of the serial read-in and read-out chains of the chip.

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patent: 3967254 (1976-06-01), Kosonocky et al.
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patent: 4103347 (1978-07-01), Barton
patent: 4211936 (1980-07-01), Kosonocky et al.
patent: 4236830 (1980-12-01), Schlig

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