Charge transfer memory

Communications: electrical – Digital comparator systems

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307238, G11C 1140

Patent

active

039672549

ABSTRACT:
Output gate electrode structure between the storage matrix and the output register of a serial-parallel-serial (SPS) charge coupled device (CCD) memory. To permit high channel packing density in the matrix, the output register can have as few as M/N stages, where M is the number of channels in the matrix and N the number of phases employed for operating the register. The gate structure transfers 1/N'th of a word at a time to the output register and while this 1/N'th of a word is being propagated out of the register, the remaining part (or parts), if any, of the word are stored while the gate structure provides a potential barrier between this stored charge and the register.

REFERENCES:
patent: 3643106 (1972-02-01), Berwin
patent: 3763480 (1973-10-01), Weimer
patent: 3797002 (1974-03-01), Brown

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