Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1998-07-01
2001-02-20
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
Reexamination Certificate
active
06191440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge transfer element. More particularly, the present invention relates to charge detection in a charge transfer device.
2. Description of the Related Art
A charge detector of a floating diffusion layer type and a charge detector of floating gate type are generally known as a charge detector applied to an output section of a charge transfer device.
In a case of the charge detector of the floating diffusion layer type, signal charges to be detected are accumulated in the floating diffusion layer provided in an output section. A voltage change of the floating diffusion layer because of the accumulation of the signal charges is amplified by a buffer amplifier provided within a chip, and outputted to an external device.
On the other hand, in a case of the charge detector of the floating gate type, the signal charges to be detected are accumulated in a transfer channel under a floating gate provided in an output section. A voltage change induced to the floating gate via a coupling capacity between a transfer channel and the floating gate because of the accumulation of the signal charges is amplified by a buffer amplifier, and outputted to an external device.
Typically, in the charge detector of the floating diffusion layer type, the floating diffusion layer is designed to have a small capacity so that a charge detection sensitivity or conversion efficiency can be improved when the signal charges are converted into an output voltage. However, there is a problem in that once the signal charges are detected, the signal charges can not be reproduced. That is, the detection is destructive detection. Also, noise referred to as a reset noise is generated.
On the other hand, the charge detector of the floating gate type typically has a smaller conversion efficiency than that of the charge detector of the floating diffused layer type. However, the charge detector of the floating gate type can detect signal charges without the destruction of the signal charges. Also, the charge detector of the floating gate type can prevent the reset noise from being generated at this time.
FIGS. 1 and 2
are conventional charge detectors of the floating gate type shown in Japanese Laid Open Patent Applications (JP-A-Showa 57-27497 and JP-A-Showa 57-86191).
The charge detectors shown in
FIGS. 1 and 2
are composed of terminals
101
,
102
,
201
,
202
and
221
for respectively supplying drive voltages; transfer gates
106
,
107
,
109
,
110
,
206
,
207
,
209
and
210
of charge transfer elements; floating gates
108
and
208
; output amplifiers
104
and
204
; wirings
103
and
203
for connecting between the floating gate and the output amplifier; a direct current (DC) bias gate
115
; a terminal
114
for applying a DC voltage to the DC bias gate; amplifier output terminals
105
and
205
; insulating films
111
and
211
; semiconductor substrates
112
and
212
; signal charges
113
and
213
; a preset transistor
224
; a terminal
223
for applying a preset pulse to a gate of the transistor
224
; and a drain terminal
222
of the transistor
224
.
The charge detector shown in
FIG. 1
is driven by a (2+½)-phase driving system in response to a driving pulse shown in
FIGS. 3A and 3B
. A stage of a charge transfer device is composed of the three gates
106
,
107
and
108
. A pulse &phgr;
A
shown in
FIG. 3A and a
pulse &phgr;
B
shown in
FIG. 3B
, which are phase-shifted from each other by 120 degrees, are applied to the terminals
101
and
102
. The offset level of the floating gate
108
is adjusted by applying a proper DC voltage V
C
to the bias gate
115
through the terminal
114
so that an offset level of the floating gate
108
is set to the approximate half of the above-mentioned pulse voltage in amplitude.
The signal charges are transferred in accordance with a usual charge transfer operation. The signal charges
113
are transferred to a region of a charge transfer channel layer directly beneath the floating gate
108
. At this time, a voltage substantially proportional to the amount of signal charges is induced to the floating gate
108
via a coupling capacity between the signal charges and the floating gate
108
. Then, the induced voltage is outputted through the output amplifier
105
to an external device as the output voltage. In this case, the signal charges are held in the charge transfer channel region directly beneath the floating gate, and never removed. Therefore, the signal charges can be transferred to a gate adjacent to the floating gate again. Thus, this charge detecting method is referred to as a non-destructively detecting method.
The charge detector shown in
FIG. 2
is driven by a (3+½)-phase driving system. A stage of the charge transfer device is composed of the four gates
206
,
207
,
208
and
209
. Pulse voltages, which are phase-shifted from each other by 90 degrees, are applied to the terminals
206
,
207
and
209
. The floating gate
208
is once set to a reference voltage by the preset transistor
224
before the signal charges are transferred. In this operation, a preset pulse is applied to the gate terminal
223
of the preset transistor
224
so that the preset transistor
224
is set to a conductive state. As a result, the bias voltage of the floating gate
208
is made equal to the reference voltage which is applied to the drain terminal
222
.
The reference voltage is usually set to the approximately half of the above-mentioned driving pulse voltage. After this preset operation is completed, the preset transistor
224
is set to a non-conductive state, and thereby the floating gate
208
is electrically separated from the external device. Similarly to the charge detector shown in
FIG. 1
, the signal charges
213
are transferred to a region of a charge transfer channel which is located directly beneath the floating gate
208
. At this time, a voltage substantially proportional to the amount of signal charges is induced to the floating gate
208
via a coupling capacity between the signal charges and the floating gate. Then, the induced voltage is outputted by the output amplifier
204
to an external device as an output voltage. This charge detecting method is also the non-destructively detecting method, similar to the charge detecting method of the charge detector shown in FIG.
1
.
FIG. 4
shows a small signal equivalent circuit in the typical charge detector of the floating gate type. The equivalent circuit can be applied to both the charge detectors shown in
FIGS. 1 and 2
. In
FIG. 4
, C
CH
is a capacity between the charge transfer channel region directly beneath the floating gate and the ground. Also, C
CP
is a coupling capacity between the floating gate and the charge transfer channel region directly beneath the floating gate. In addition, C
FG
is a capacity between the floating gate and the ground. The capacity C
FG
includes all the parasitic capacities to the floating gate, such as the capacity of the wire for connecting the floating gate and the output amplifier, the input capacity of the output amplifier.
Now, it is assumed that the amount of signal charges to be transferred is Q. In this case, a signal voltage &Dgr;V induced to the floating gate is given by the following equation.
V=Q/C
S
C
S
=C
CH
+C
FG
+C
CH
×C
FG
/C
CP
Hereafter, the capacity C
S
represented by the above equation is referred to as a charge detection capacity.
In order to reduce the charge detection capacity of the charge detector of the floating gate type so that a charge detection sensitivity can be improved, it is necessary to reduce the capacity C
CH
and the capacity C
FG
. In addition, it is necessary to increase the coupling capacity C
CP
between the floating gate and the channel region directly beneath the floating gate.
However, even if the size of the floating gate is decreased so as to reduce the capacities C
CH
and C
FG
, there is a limitation on a manufacturing condition. Moreover, even i
Mutoh Nobuhiko
Nakano Takashi
Lee Calvin
NEC Corporation
Smith Matthew
Young and Thompson
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