Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-10-27
2002-07-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S251000, C257S912000, C257S238000, C257S239000, C257S219000, C257S229000, C257S246000, C257S248000, C257S183100, C257S231000, C438S075000, C438S144000, C438S148000
Reexamination Certificate
active
06417531
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a charge transfer device and, more particularly, to a charge transfer device with a floating diffusion amplifier.
DESCRIPTION OF THF RELATED ART
A typical example of the charge transfer device is disclosed in IEDM Technical Digest, 1973, page 24 and IEDM Technical Digest, 1974, page 55.
FIGS. 1 and 2
illustrate the prior art charge transfer device. The prior art charge transfer device is fabricated on a p-type semiconductor substrate
101
. In a major surface portion of the p-type semiconductor substrate
101
are formed lightly-doped n-type impurity regions
102
and n-type impurity regions
103
which are alternated with one another. The rightmost n-type impurity region is decreased in width, and is contiguous to the rightmost lightly-doped n-type impurity region. An n-type floating diffusion region
112
is provided between the rightmost lightly-doped n-type impurity region and a heavily-doped n-type impurity region
104
. A heavily-doped p-type impurity region
105
surrounds the above-described n-type impurity regions
102
/
103
/
104
and the n-type floating diffusion region
112
.
The major surface of the p-type semiconductor substrate
101
is covered with an insulating layer
106
, and charge transfer electrodes
107
a
/
107
b
/
207
a
and
108
a
/
108
b
/
208
a
are electrically isolated from one another in the insulating layer
106
. In order to make the charge transfer electrodes
107
a
/
107
b
/
207
a
/
108
a
/
108
b
/
208
a
clear, any hatching line is not drawn in the cross section of the insulating layer
106
shown in FIG.
2
.
The charge transfer electrodes
107
a
/
107
b
/
207
a
are respectively provided over the n-type impurity regions
103
, and the charge transfer electrodes
108
a
/
108
b
are provided over the lightly doped n-type impurity regions
102
. The charge transfer electrodes
107
a
/
107
b
/
207
a
are partially overlapped with the charge transfer electrodes
108
a
/
108
b
. A gate electrode
109
is provided over the rightmost lightly-doped n-type impurity region.
A clock signal &PHgr;
1
is supplied from a metal line
111
to the charge transfer electrodes
107
a
/
108
a
/
207
a
/
208
a
, and a clock signal &PHgr;
2
is supplied to the charge transfer electrodes
107
b
/
108
b
. A constant voltage VOG is supplied to the gate electrode
109
. Thus, the charge transfer electrodes
107
a
,
207
a
and
107
b
are respectively paired with the adjacent charge transfer electrodes
108
a
,
208
a
and
108
b
, and the clock signals &PHgr;
1
and &PHgr;
2
are selectively supplied to the charge transfer electrode pairs
107
a
/
108
a
,
207
a
/
208
a
and
107
b
/
108
b.
A gate electrode
110
is provided over the lightly-doped n-type impurity region between the floating diffusion region
112
and the heavily-doped n-type impurity region
104
. A reset signal &PHgr;R is supplied to the gate electrode
110
, and the floating diffusion region
112
is connected to an output circuit (not shown). The output circuit is implemented by a source follower, and the source follower achieves the impedance conversion.
FIGS. 3A
,
3
B and
3
C illustrate potential wells created in the prior art charge transfer device during a charge transfer. Firstly, the reset signal &PHgr;R is applied to the gate electrode
110
. Then, the potential barrier is removed from the lightly-doped n-type region under the gate electrode
110
as shown in
FIG. 3A
, and electric charge flows from the floating diffusion region
112
to the heavily-doped n-type impurity region
104
. As a result, the floating diffusion region
112
becomes equal to the reset voltage VR. The clock signal &PHgr;
1
is in the high level VH, and the other clock signal &PHgr;
2
is in the low level VL (see FIG.
4
). Charge packets e
1
and e
2
are accumulated in the potential well under the charge transfer electrode
208
a
and in the potential well under the charge transfer electrode
108
a
, respectively.
Subsequently, the reset signal &PHgr;R is removed from the gate electrode
110
, and the potential barrier separates the floating diffusion region
112
from the heavily-doped n-type impurity region
104
. The clock signals &PHgr;
1
and &PHgr;
2
are maintained at time t
1
, and the charge packets e
1
and e
2
are still accumulated in the potential well under the charge transfer electrode
208
a
and in the potential well under the charge transfer electrode
108
a
, respectively.
The clock signals &PHgr;
1
and &PHgr;
2
are respectively changed to the low level VL and the high level VH at time t
2
. Then, the potential well is created under the leftmost charge transfer electrode
108
b
, and a charge packet e
3
flows into the potential well. The potential barrier is removed from the lightly-doped n-type impurity region under the charge transfer electrode
107
b
, and a potential well is created in the n-type impurity region under the charge transfer electrode
108
b
. Then, the charge packet e
2
flows into the potential well in the n-type impurity region under the charge transfer electrode
108
b
as shown in FIG.
3
C. Moreover, the bottom of the potential well under the charge transfer electrode
208
a
exceeds the potential barrier in the rightmost lightly-doped n-type impurity region under the gate electrode
109
, and the charge packet e
1
flows into the floating diffusion region
112
.
The charge packet e
1
varies the potential level in the floating diffusion region
112
, and the potential variation is detected by the output circuit. The output circuit produces an output signal, the voltage level V of which is given as
V=Q/C×G
where Q is the amount of charge of the charge packet e
1
, C is a capacitance coupled to the floating diffusion
112
and G is a voltage gain. Finally, the reset signal VR is applied to the gate electrode
110
, again, and the potential barrier is removed from the lightly-doped n-type impurity region under the gate electrode
110
. The floating diffusion region
112
is reset to the reset voltage VR. Thus, the charge packets e
1
, e
2
and e
3
are stepwise transferred to the floating diffusion region
112
, and the output circuit produces the output signal from the potential variation in the floating diffusion region
112
.
It is desirable to widely vary the potential level V of the output signal. As will be understood from the above equation, the smaller the capacitance C, the wider the variation of the potential level V. For this reason, the floating diffusion region
112
is much narrower than the n-type impurity regions
103
and
102
(compare the channel width W with the channel width W′ FIG.
1
). This is the reason the rightmost n-type impurity region contracts toward the rightmost lightly-doped n-type impurity region. As a result, the charge transfer electrode
208
a
has length L′ longer than length L of the other charge transfer electrodes
108
a
and
108
b
, and signal charge accumulated around the oblique side lines flows over length L″ greater than length L′.
As described hereinbefore, the charge packets e
1
, e
2
and e
3
are transferred from the potential well to the next potential well in response to the clock signals &PHgr;
1
and &PHgr;
2
. While the clock signal &PHgr;
2
is staying at the high level VH, the charge packets are transferred from the potential well to the next potential well. When the clock signal &PHgr;
2
is recovered from the low level VL to the high level VH, the potential well is isolated from the next potential well, and the charge transfer is completed. If the clock signal &PHgr;
2
stays at the high level VH for a sufficiently long time, the charge packet is perfectly transferred to the next potential well without any residual charge. However, a high-speed charge transfer is required for a high-dense image pick-up device. As described hereinbefore, the signal charge in the central area of the leftmost n-type impurity region is moved over the length L′, and the signal charge in the peripheral area is moved over the length L″
Meier Stephen D.
Mitchell James
NEC Corporation
Soloway Hayes
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